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參數(shù)資料
| 型號： | AD9240 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit, 10 MSPS Monolithic A/D Converter |
| 中文描述： | 完整的14位，10 MSPS的單片機(jī)的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 328K |
| 代理商： | AD9240 |
AD9240
REV. A
–8–
CLOCK FREQUENCY – MHz
S
80
20
1
20
10
70
60
50
40
30
10
0
R
BIAS
= 10k
V
R
BIAS
= 20k
V
R
BIAS
= 200k
V
R
BIAS
=
V
R
BIAS
=
2k
V
Figure 21. SINAD vs. Clock Frequency for Varying R
BIAS
Values (V
CM
= 2.5 V, A
IN
= –0.5 dB, 5 V Span, f
IN
= f
CLK
/2)
CLOCK FREQUENCY – MHz
P
400
100
2
20
4
6
8
10
12
14
16
18
350
300
250
200
150
R
BIAS
= 1.7k
V
R
BIAS
= 2k
V
R
BIAS
= 2.5k
V
R
BIAS
= 3.3k
V
R
BIAS
= 5k
V
R
BIAS
= 10k
V
R
BIAS
= 100k
V
Figure 22. Power Dissipation vs. Clock Frequency for
Varying R
BIAS
Values
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 23, a simplified model of the AD9240, highlights the rela-
tionship between the analog inputs, VINA, VINB, and the ref-
erence voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF defines
the maximum input voltage to the A/D
core. The minimum input
voltage to the A/D
core is automatically defined to be –VREF.
V
CORE
VINA
VINB
+VREF
–VREF
A/D
CORE
14
AD9240
Figure 23. Equivalent Functional Input Circuit
INTRODUCTION
The AD9240 uses a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D con-
nected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the differ-
ence between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash er-
rors. The last stage simply consists of a flash A/D.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be con-
figured to interface with +5 V or +3.3 V logic families.
The AD9240 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value, and should be minimized.
Speed/Power Programmability
The AD9240’s maximum conversion rate and associated power
dissipation can be set using the part’s BIAS pin. A simplified
diagram of the on-chip circuitry associated with the BIAS pin is
shown in Figure 20.
AD9240
BIAS
R
BIAS
I
FIXED
ADC
BIAS
Figure 20.
The value of R
BIAS
can be varied over a limited range to set the
maximum sample rate and power dissipation of the AD9240. A
typical plot of S/(N+D) @ f
IN
= Nyquist vs. f
CLK
at varying
R
BIAS
is shown in Figure 21. A similar plot of power vs. f
CLK
at varying R
BIAS
is shown in Figure 22. These plots indicate
typical performance vs. R
BIAS
. Note that all other plots and
specifications in this data sheet reflect performance at a fixed
R
BIAS
= 2 k
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9240AS | Complete 14-Bit, 10 MSPS Monolithic A/D Converter |
| AD9240EB | Complete 14-Bit, 10 MSPS Monolithic A/D Converter |
| AD9241 | Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter |
| AD9241AS | RES., MF, 2K, 1%, 1/4W |
| AD9241EB | Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9240AS | 功能描述:IC ADC 14BIT 10MSPS 44-MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9240ASRL | 功能描述:IC ADC 14BIT 10MSPS 44-MQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9240ASZ | 功能描述:IC ADC 14BIT 10MSPS 44-MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD9240ASZRL | 功能描述:IC ADC 14BIT 10MSPS 44-MQFP TR RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9240EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 14-Bit, 10 MSPS Monolithic A/D Converter |
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