參數(shù)資料
型號(hào)： AD9238BSTRL-65
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 12-Bit, 20/40/65 MSPS Dual A/D Converter
中文描述： 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP64
封裝： LEAD FREE, MS-026-BBD, LQFP-64
文件頁(yè)數(shù)： 2/24頁(yè)
文件大?。?/td> 1737K
代理商： AD9238BSTRL-65
–2–
AD9238–SPECIFICATIONS
DC SPECIFICATIONS
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input,
1.0 V Internal Reference, T
MIN
to T
MAX
, un ess oth er wise noted.)
Parameter
Test AD9238BST-20 AD9238BST-40 AD9238BST-65
Temp Level Min Typ Max Min Typ
Max Min Typ
Max
Unit
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
TEMPERATURE DRIFT
Offset Error
Gain Error
1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
Input Span = 1 V
Input Span = 2.0 V
ANALOG INPUT
Input Span = 1.0 V
Input Span = 2.0 V
Input Capacitance
3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
PSRR
POWER CONSUMPTION
DC Input
4
Sine Wave Input
2
Standby Power
5
MATCHING CHARACTERISTICS
Offset Error
Gain Error
Full VI 12
12
12
Bits
Full VI 12
Full VI
Full IV
Full V
25 C I
Full V
25 C I
12
±0.30 ±1.2
±0.30 ±2.2
±0.35
±0.35 ±0.9
±0.45
±0.40 ±1.4
±0.50 ±1.1
±0.50 ±2.4
±0.35
±0.35 ±0.8
±0.60
±0.50 ±1.4
12
±0.50 ±1.1
±0.50 ±2.5
±0.35
±0.35 ±1.0
±0.70
±0.55 ±1.75 LSB
Bits
% FSR
% FSR
LSB
LSB
LSB
Full V
Full V
±2
±12
±2
±12
±3
±12
ppm/°C
ppm/°C
Full VI
Full V
Full V
Full V
±5 ±35
0.8
±2.5
0.1
±5
0.8
±2.5
0.1
±35
±5
0.8
±2.5
0.1
±35
mV
mV
mV
mV
25 C V
25 C V
0.54
0.27
0.54
0.27
0.54
0.27
LSB rms
LSB rms
Full IV
Full IV
Full V
Full V
1
2
7
7
1
2
7
7
1
2
7
7
V p-p
V p-p
pF
k
Full IV 2.7
Full IV 2.25 3.0 3.6 2.25 3.0
3.0 3.6 2.7
3.0
3.6 2.7
3.6 2.25 3.0
3.0
3.6
3.6
V
V
Full V
Full V
Full V
60
4
±0.01
110
10
±0.01
200
14
±0.01
mA
mA
% FSR
Full V
Full VI
Full V
180
190 212
2.0
330
360
2.0
397
600
640
2.0
698
mW
mW
mW
Full V
Full V
±0.1
±0.05
±0.1
±0.05
±0.1
±0.05
% FSR
% FSR
NOTES
1
Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 2 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
REV. A
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