參數(shù)資料
型號(hào): AD9238BSTRL-20
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 12-Bit, 20/40/65 MSPS Dual A/D Converter
中文描述: 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP64
封裝: MS-026-BBD, LQFP-64
文件頁(yè)數(shù): 6/24頁(yè)
文件大?。?/td> 1737K
代理商: AD9238BSTRL-20
AD9238
–6–
PIN FUNCTION DESCRIPTIONS
Description
Analog Input Pin (+) for Channel A
Analog Input Pin (–) for Channel A
Analog Input Pin (+) for Channel B
Analog Input Pin (–) for Channel B
Differential Reference (+) for Channel A
Differential Reference (–) for Channel A
Differential Reference (+) for Channel B
Differential Reference (–) for Channel B
Voltage Reference Input/Output
Reference Mode Selection
Clock Input Pin for Channel B
Clock Input Pin for Channel A
Enable Duty Cycle Stabilizer (DCS) Mode
Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement)
Power-Down Function Selection for Channel B (Active High)
Power-Down Function Selection for Channel A (Active High)
Output Enable Bit for Channel B
Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus)
Channel A Data Output Bits
Channel B Data Output Bits
Out-of-Range Indicator for Channel B
Out-of-Range Indicator for Channel A
Shared Reference Control Bit (Low for Independent Reference Mode,
High for Shared Reference Mode)
Data Multiplexed Mode. (See description for how to enable; high setting disables
output data Multiplexed mode).
Analog Power Supply
Analog Ground
Digital Output Ground
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum
0.1 μF capacitor. Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF.
Do Not Connect Pins. Should be left floating.
Pin Number
2
3
15
14
6
7
11
10
8
9
18
63
19
20
21
60
22
59
44–51, 54–57
25–27, 30–38
39
58
62
Mnemonic
VIN+_A
VIN–_A
VIN+_B
VIN–_B
REFT_A
REFB_A
REFT_B
REFB_B
VREF
SENSE
CLK_B
CLK_A
DCS
DFS
PDWN_B
PDWN_A
OEB_B
OEB_A
D0_A (LSB)–D11_A (MSB)
D0_B (LSB)–D11_B (MSB)
OTR_B
OTR_A
SHARED_REF
61
MUX_SELECT
5, 12, 17, 64
1, 4, 13, 16
28, 40, 53
29, 41, 52
AVDD
AGND
DRGND
DRVDD
23, 24, 42, 43
DNC
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60
55 54 53 52 51 50 49
59 58 57 56
PIN 1
64-LEAD LQFP
TOP VIEW
(Not to Scale)
D4_A
D3_A
D2_A
D1_A
D0_A
DNC
DNC
DRVDD
DRGND
OTR_B
D11_B (MSB)
D10_B
D9_B
D8_B
D7_B
D6_B
AD9238
AGND
VIN+_A
VIN–_A
AGND
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
AGND
VIN–_B
VIN+_B
AGND
AVDD
C
S
M
O
D
D
D
D
D
D
D
D
C
D
D
P
O
D
D
D
D
D
D
D
D
D
A
D
A
P
O
D
DNC = DO NOT CONNECT
REV. A
相關(guān)PDF資料
PDF描述
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