參數(shù)資料
型號(hào): AD9236BRUZRL7-80
廠商: Analog Devices Inc
文件頁(yè)數(shù): 33/36頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 80MSPS 28TSSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 366mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
AD9236
Data Sheet
Rev. C | Page 6 of 36
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
Parameter
Temp
Test Level
AD9236BRU/AD9236BCP
Unit
Min
Typ
Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
VI
80
MSPS
Minimum Conversion Rate
Full
V
1
MSPS
CLK Period
Full
V
12.5
ns
CLK Pulse Width High1
Full
V
4.0
ns
CLK Pulse Width Low1
Full
V
4.0
ns
DATA OUTPUT PARAMETERS
Output Propagation Delay (tPD)2
Full
V
3.5
ns
Pipeline Delay (Latency)
Full
V
7
Cycles
Aperture Delay (tA)
Full
V
1.0
ns
Aperture Uncertainty (Jitter, tJ)
Full
V
0.3
ps rms
Wake-Up Time3
Full
V
7
ms
OUT OF RANGE RECOVERY TIME
Full
V
2
Cycles
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3 Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
tA
2.0ns MIN
tPD = 6.0ns MAX
03066-0-002
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
ANALOG
INPUT
CLK
DATA
OUT
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram
Table 5. Explanation of Test Levels
Test Level
Definitions
I
100% production tested.
II
100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
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