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| 型號(hào)： | AD9236BCPZRL7-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 80MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 366mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
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AD9236
Data Sheet
Rev. C | Page 14 of 36
THEORY OF OPERATION
The AD9236 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections,
consisting of a 4-bit first stage followed by eight 1.5-bit stages
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 12-bit result
in the digital correction logic. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT AND REFERENCE OVERVIEW
The analog input to the AD9236 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal. The
SHA input can support a wide common-mode range (VCM)
and maintain excellent performance, as shown in Figure 26. An
input common-mode voltage of midsupply minimizes signal-
dependant errors and provides optimum performance.
100
S
NR/S
F
DR
(dBc
)
50
55
60
65
70
75
80
85
90
95
0.5
1.0
1.5
2.0
2.5
3.0
COMMON-MODE LEVEL (V)
03066-0-016
SFDR (2.5MHz)
SFDR (39MHz)
SNR (2.5MHz)
SNR (39MHz)
Figure 26. SNR, SFDR vs. Common-Mode Level
Referring to Figure 27, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. In addition, a small shunt capacitor
can be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependant upon
the application. In IF undersampling applications, any shunt
capacitors should be reduced or removed. In combination with the
driving source impedance, they would limit the input bandwidth.
03066-0-012
H
VIN+
VIN–
CPAR
T
5pF
T
Figure 27. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as follows:
REFT = (AVDD + VREF)
REFB = (AVDD + VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from the previous equations that the REFT and
REFB voltages are symmetrical about the midsupply voltage and,
by definition, the input span is twice the value of the VREF voltage.
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9236 set
to the largest input span of 2 V p-p. The relative SNR degradation is
3 dB when changing from 2 V p-p mode to 1 V p-p mode.
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| AD9236BRUZ-80 | 功能描述:IC ADC 12BIT 80MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9236BRUZRL7-80 | 功能描述:IC ADC 12BIT 80MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
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