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參數(shù)資料
| 型號(hào)： | AD9235BRU-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20/40/65 MSPS 3 V A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MO-153-AE, TSSOP-28 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 1181K |
| 代理商： | AD9235BRU-40 |
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REV. B
–17–
AD9235
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9235 can output data in either
offset binary or twos complement format. There is also a provision
for enabling or disabling the clock duty cycle stabilizer (DCS).
The MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined below.
Table II. Mode Selection
MODE
Voltage
Data
Format
Duty Cycle
Stabilizer
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
Twos Complement
Twos Complement
Offset Binary
Offset Binary
Disabled
Enabled
Enabled
Disabled
The MODE pin is internally pulled down to AGND by a
20 k
resistor.
TSSOP EVALUATION BOARD
The AD9235 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially,
through an AD8138 driver or a transformer, or single-ended.
Separate power pins are provided to isolate the DUT from the
support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 16 shows the typical bench characterization setup used to
evaluate the ac performance of the AD9235. It is critical that
signal sources with very low phase noise (<1 ps rms jitter) be used
to realize the ultimate performance of the converter. Proper
filtering of the input signal, to remove harmonics and lower the
integrated noise at the input, is also necessary to achieve the
specified noise performance.
The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance (i.e., IF undersampling
characterization). It allows the user to apply a clock input signal that
is 4
×
the target sample rate of the AD9235. A low-jitter, differential
divide-by-4 counter, the MC100LVEL33D, provides a 1
×
clock
output that is subsequently returned back to the CLK input via
JP9. For example, a 260 MHz signal (sinusoid) will be divided
down to a 65 MHz signal for clocking the ADC. Note that R1 must
be removed with the AUXCLK interface. Lower jitter is often
achieved with this interface since many RF signal generators
display improved phase noise at higher output frequencies and the
slew rate of the sinusoidal output signal is 4
×
that of a 1
×
signal
of equal amplitude.
Complete schematics and layout plots follow and demonstrate the
proper routing and grounding techniques that should be applied
at the system level.
LFCSP EVALUATION BOARD
The typical bench setup used to evaluate the ac performance
of the AD9235 is similar to the TSSOP Evaluation Board
connections (refer to the schematics for connection details).
The AD9235 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input con-
figuration can be selected by proper connection of various
jumpers (refer to the schematics).
An alternative differential analog input path using an AD8351
op amp is included in the layout but is not populated in pro-
duction. Designers interested in evaluating the op amp with
the ADC should remove C15, R12, and R3 and populate the
op amp circuit. The passive network between the AD8351
outputs and the AD9235 allows the user to optimize the fre-
quency response of the op amp for the application.
DATA
CAPTURE
AND
PROCESSING
3V
–
+
3V
–
+
3V
–
+
3V
–
+
REFIN
10MHz
REFOUT
HP8644, 2V p-p
SIGNAL SYNTHESIZER
HP8644, 2V p-p
CLOCK SYNTHESIZER
BAND-PASS
FILTER
S4
XFMR
INPUT
S1
CLOCK
AVDD
DUT
AVDD
GND
GND DUT
DRVDD
DVDD
AD9235
TSSOP EVALUATION BOARD
J1
CLOCK
DIVIDER
Figure 16. TSSOP Evaluation Board Connections
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