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| 型號： | AD9235BCPZ-20 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SGL 20MSPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 90mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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Data Sheet
AD9235
Rev. D | Page 19 of 40
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 41 shows the typical drift characteris-
tics of the internal reference in both 1 V and 0.5 V modes.
02461-041
TEMPERATURE (°C)
80
–40 –30 –20 –10
0
10
20
30
40
50
60
70
VREF
ERROR
(%)
1.2
1.0
0.8
0.6
0.4
0.2
0
VREF = 1.0V
VREF = 0.5V
Figure 41. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 k load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
If the internal reference of the AD9235 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 42
depicts how the internal reference voltage is affected by loading.
02461-042
LOAD (mA)
3.0
0
0.5
1.0
1.5
2.0
2.5
ERROR
(%)
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
0.5V ERROR (%)
1V ERROR (%)
Figure 42. VREF Accuracy vs. Load
OPERATIONAL MODE SELECTION
As discussed earlier, the AD9235 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock DCS. The MODE pin is a multi-
level input that controls the data format and DCS state. The
input threshold values and corresponding mode selections are
outlined in Table 8.
Table 8. Mode Selection
MODE Voltage
Data Format
Duty Cycle Stabilizer
AVDD
Twos Complement
Disabled
2/3 AVDD
Twos Complement
Enabled
1/3 AVDD
Offset Binary
Enabled
AGND (Default)
Offset Binary
Disabled
The MODE pin is internally pulled down to AGND by a 20 k
resistor.
TSSOP EVALUATION BOARD
The AD9235 evaluation board provides the support circuitry
required to operate the ADC in its various modes and configu-
rations. The converter can be driven differentially, through an
AD8138 driver or a transformer, or single-ended. Separate pow-
er pins are provided to isolate the DUT from the support cir-
cuitry. Each input configuration can be selected by proper con-
nection of various jumpers (refer to the schematics). Figure 43
shows the typical bench characterization setup used to evaluate
the ac performance of the AD9235. It is critical that signal
sources with very low phase noise (<1 ps rms jitter) be used to
realize the ultimate performance of the converter. Proper filter-
ing of the input signal, to remove harmonics and lower the inte-
grated noise at the input, is also necessary to achieve the speci-
fied noise performance.
The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance, i.e., IF undersampling
characterization. It allows the user to apply a clock input signal
that is 4× the target sample rate of the AD9235. A low-jitter,
differential divide-by-4 counter, the MC100LVEL33D, provides
a 1× clock output that is subsequently returned back to the CLK
input via JP9. For example, a 260 MHz signal (sinusoid) is
divided down to a 65 MHz signal for clocking the ADC. Note
that R1 must be removed with the AUXCLK interface. Lower
jitter is often achieved with this interface since many RF signal
generators display improved phase noise at higher output
frequencies and the slew rate of the sinusoidal output signal is
4× that of a 1× signal of equal amplitude.
Complete schematics and layout plots follow and demonstrate
the proper routing and grounding techniques that should be
applied at the system level.
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