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參數(shù)資料
| 型號： | AD9226ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 65MSPS 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 475mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
REV. B
–3–
AD9226
DIGITAL SPECIFICATIONS
Parameters
Temp
Test Level
Min
Typ
Max
Unit
LOGIC INPUTS (Clock, DFS
1, Duty Cycle1, and
Output Enable
1)
High-Level Input Voltage
Full
IV
2.4
V
Low-Level Input Voltage
Full
IV
0.8
V
High-Level Input Current (VIN = AVDD)
Full
IV
–10
+10
A
Low-Level Input Current (VIN = 0 V)
Full
IV
–10
+10
A
Input Capacitance
Full
V
5
pF
Output Enable
1
Full
IV
V
LOGIC OUTPUTS (With DRVDD = 5 V)
High-Level Output Voltage (IOH = 50
A)
Full
IV
4.5
V
High-Level Output Voltage (IOH = 0.5 mA)
Full
IV
2.4
V
Low-Level Output Voltage (IOL = 1.6 mA)
Full
IV
0.4
V
Low-Level Output Voltage (IOL = 50
A)
Full
IV
0.1
V
Output Capacitance
5pF
LOGIC OUTPUTS (With DRVDD = 3 V)
High-Level Output Voltage (IOH = 50
A)
Full
IV
2.95
V
High-Level Output Voltage (IOH = 0.5 mA)
Full
IV
2.80
V
Low-Level Output Voltage (IOL = 1.6 mA)
Full
IV
0.4
V
Low-Level Output Voltage (IOL = 50
A)
Full
IV
0.05
V
NOTES
1LQFP package.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameters
Temp
Test Level
Min
Typ
Max
Unit
Max Conversion Rate
Full
VI
65
MHz
Clock Period
1
Full
V
15.38
ns
CLOCK Pulsewidth High
2
Full
V
3
ns
CLOCK Pulsewidth Low
2
Full
V
3
ns
Output Delay
Full
V
3.5
7
ns
Pipeline Delay (Latency)
Full
V
7
Clock Cycles
Output Enable Delay
3
Full
V
15
ns
NOTES
1The clock period may be extended to 10
s without degradation in specified performance @ 25°C.
2When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.
3LQFP package.
Specifications subject to change without notice.
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)
(TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n
ANALOG
INPUT
CLOCK
DATA
OUT
n–8
n–7
n–6
n–5
n–4
n–3
n–2
n+1
n
n–1
TOD = 7.0 MAX
3.5 MIN
Figure 1. Timing Diagram
DRVDD
2
05
– .
DRVDD
2
05
+ .
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| AD9226ASTZRL | 功能描述:IC ADC 12BIT 65MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
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