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參數(shù)資料
| 型號(hào)： | AD9226ARSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 65MSPS 28-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 475mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
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REV. B
AD9226
–20–
Digital Output Driver Considerations
The AD9226 output drivers can be configured to interface with
5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families. However,
large drive currents tend to cause glitches on the supplies and may
affect converter performance. Applications requiring the ADC to
drive large capacitive loads or large fan outs may require external
buffers or latches.
OEB Function (Three-State)
The LQFP-packaged AD9226 has Three-State (OEB) ability. If
the OEB pin is held low, the output data drivers are enabled. If
the OEB pin is high, the output data drivers are placed in a high
impedance state. It is not intended for rapid access to buss.
Clock Input Considerations
High-speed, high-resolution ADCs are sensitive to the quality of
the clock input. The clock input should be treated as an analog
signal in cases where aperture jitter may affect the dynamic
performance of the AD9226. Power supplies for clock drivers
should be separated from the ADC output driver supplies to
avoid modulating the clock signal with digital noise. Low-jitter
crystal controlled oscillators make the best clock sources.
The quality of the clock input, particularly the rising edge, is
critical in realizing the best possible jitter performance of the
part. Faster rising edges often have less jitter.
Clock Input and Power Dissipation
Most of the power dissipated by the AD9226 is from the analog
power supplies. However, lower clock speeds will reduce digital
current. Figure 16 shows the relationship between power and
clock rate.
SAMPLE RATE – Msps
515
POWER
DISSIPATION
–
mW
250
200
25
35
300
350
400
450
500
550
600
45
55
65
75
DRVDD = 3V
DRVDD = 5V
Figure 16. Power Consumption vs. Sample Rate
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high-speed, high-resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
It is important to design a layout that prevents noise from cou-
pling onto the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. While the AD9226 features separate analog
and driver ground pins, it should be treated as an analog com-
ponent. The AVSS and DRVSS pins must be joined together
directly under the AD9226. A solid ground plane under the
ADC is acceptable if the power and ground return currents are
carefully managed.
0.1 F
AVDD
AVSS
AD9226
10 F
Figure 17. Analog Supply Decoupling
Analog and Digital Driver Supply Decoupling
The AD9226 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals. In general, AVDD (analog power) should be
decoupled to AVSS (analog ground). The AVDD and AVSS
pins are adjacent to one another. Also, DRVDD (digital power)
should be decoupled to DRVDD (digital ground). The decoupling
capacitors (especially 0.1
F) should be located as close to the
pins as possible. Figure 17 shows the recommended decoupling
for the pair of analog supplies; 0.1
F ceramic chip and 10 F
tantalum capacitors should provide adequately low impedance
over a wide frequency range.
0.1 F
CML
AD9226
0.1 F
VR
Figure 18. CML Decoupling (LQFP)
Bias Decoupling
The CML and VR are analog bias points used internally by the
AD9226. These pins must be decoupled with at least a 0.1
F
capacitor as shown in Figure 18. The dc level of CML is approxi-
mately AVDD/2. This voltage should be buffered if it is to be
used for any external biasing. CML and VR outputs are only
available in the LQFP package.
0.1 F
DRVDD
DRVSS
AD9226
10 F
Figure 19. Digital Supply Decoupling
CML
The LQFP-packaged AD9226 has a midsupply reference point.
This midsupply point is used within the internal architecture of
the AD9226 and must be decoupled with a 0.1
F capacitor. It
will source or sink a load of up to 300
A. If more current is
required, it should be buffered with a high impedance amplifier.
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