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參數(shù)資料
| 型號： | AD9226-LQFP-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit, 65 MSPS ADC Converter |
| 中文描述： | 完整的12位，65 MSPS的ADC轉(zhuǎn)換 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 1480K |
| 代理商： | AD9226-LQFP-EB |
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REV. 0
–3–
AD9226
DIGITAL SPECIFICATIONS
Parameters
LOGIC INPUTS (Clock, DFS
1
, Duty Cycle
1
,
and
Output Enable
1
)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current (V
IN
= AVDD)
Low-Level Input Current (V
IN
= 0 V)
Input Capacitance
Output Enable
1
Temp
Test Level
Min
Typ
Max
Unit
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
IV
2.4
V
V
μ
A
μ
A
pF
V
0.8
+10
+10
–10
–10
5
LOGIC OUTPUTS (With DRVDD = 5 V)
High-Level Output Voltage (I
OH
= 50
μ
A)
High-Level Output Voltage (I
OH
= 0.5 mA)
Low-Level Output Voltage (I
OL
= 1.6 mA)
Low-Level Output Voltage (I
OL
= 50
μ
A)
Output Capacitance
Full
Full
Full
Full
IV
IV
IV
IV
4.5
2.4
V
V
V
V
pF
0.4
0.1
5
LOGIC OUTPUTS (With DRVDD = 3 V)
High-Level Output Voltage (I
OH
= 50
μ
A)
High-Level Output Voltage (I
OH
= 0.5 mA)
Low-Level Output Voltage (I
OL
= 1.6 mA)
Low-Level Output Voltage (I
OL
= 50
μ
A)
Full
Full
Full
Full
IV
IV
IV
IV
2.95
2.80
V
V
V
V
0.4
0.05
NOTES
1
LQFP package.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameters
Temp
Test Level
Min
Typ
Max
Unit
Max Conversion Rate
Clock Period
1
CLOCK Pulsewidth High
2
CLOCK Pulsewidth Low
2
Output Delay
Pipeline Delay (Latency)
Output Enable Delay
3
Full
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
V
65
15.38
3
3
3.5
MHz
ns
ns
ns
ns
Clock Cycles
ns
7
7
15
NOTES
1
The clock period may be extended to 10
μ
s without degradation in specified performance @ 25
°
C.
2
When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.
3
LQFP package.
Specifications subject to change without notice.
(AVDD = 5 V, DRVDD = 3 V, f
SAMPLE
= 65 MSPS, VREF
= 2.0 V, T
MIN
to T
MAX
, unless otherwise noted.)
(T
MIN
to T
MAX
with AVDD = 5 V, DRVDD = 3 V, C
L
= 20 pF)
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n
ANALOG
INPUT
CLOCK
DATA
OUT
n–8
n–7
n–6
n–5
n–4
n–3
n–2
n+1
n
n–1
TOD = 7.0 MAX
3.5 MIN
Figure 1. Timing Diagram
DRVDD
2
0 5
–
.
DRVDD
2
0 5
+
.
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|---|---|
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| AD9228-65EB | 制造商:Analog Devices 功能描述: |
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