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參數(shù)資料
| 型號： | AD9222BCPZRL7-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 8-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 6/56頁 |
| 文件大?。?/td> | 2026K |
| 代理商： | AD9222BCPZRL7-40 |
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AD9222
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Rev. 0 | Page 6 of 56
Table 4.
Parameter
1
CLOCK
2
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (t
EH
)
Clock Pulse Width Low (t
EL
)
OUTPUT PARAMETERS
2
, 3
Propagation Delay (t
PD
)
Rise Time (t
R
) (20% to 80%)
Fall Time (t
F
) (20% to 80%)
FCO Propagation Delay (t
FCO
)
DCO Propagation Delay (t
CPD
)
4
AD9222-40
Typ
12.5
12.5
2.3
300
300
2.3
t
FCO
+
(t
SAMPLE
/24)
(t
SAMPLE
/24)
(t
SAMPLE
/24)
±50
AD9222-50
Typ
10.0
10.0
2.3
300
300
2.3
t
FCO
+
(t
SAMPLE
/24)
(t
SAMPLE
/24)
(t
SAMPLE
/24)
±50
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
40
1.5
1.5
Max
10
3.1
3.1
Min
50
1.5
1.5
Max
10
3.1
3.1
DCO to Data Delay (t
DATA
)
4
DCO to FCO Delay (t
FRAME
)
4
Data to Data Skew
(t
DATA-MAX
t
DATA-MIN
)
Wake-Up Time (Standby)
Wake-Up Time (Power Down)
Pipeline Latency
Full
Full
Full
(t
SAMPLE
/24) 300
(t
SAMPLE
/24) 300
(t
SAMPLE
/24) + 300
(t
SAMPLE
/24) + 300
±200
(t
SAMPLE
/24) 300
(t
SAMPLE
/24) 300
(t
SAMPLE
/24) + 300
(t
SAMPLE
/24) + 300
±200
ps
ps
ps
25°C
25°C
Full
600
375
8
600
375
8
ns
μs
CLK
cycles
ps
ps rms
CLK
cycles
APERTURE
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
25°C
25°C
25°C
750
<1
1
750
<1
1
1
See the AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation
, for a complete set of definitions and how these tests were completed.
2
Can be adjusted via the SPI interface.
3
Measurements were made using a part soldered to FR4 material.
4
t
SAMPLE
/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
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