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參數(shù)資料
| 型號： | AD9219BCPZ-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| 中文描述： | 4-CH 10-BIT FLASH METHOD ADC, SERIAL ACCESS, QCC48 |
| 封裝： | 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 6/52頁 |
| 文件大?。?/td> | 1571K |
| 代理商： | AD9219BCPZ-40 |
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AD9219
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 0.5 dBFS, unless otherwise noted.
Table 4.
AD9219-40
Parameter
1
Temp
Min
Typ
CLOCK
2
Maximum Clock Rate
Full
40
Minimum Clock Rate
Full
Clock Pulse Width High (t
EH
)
Full
12.5
Clock Pulse Width Low (t
EL
)
Full
12.5
OUTPUT PARAMETERS
2
Propagation Delay (t
PD
)
Full
2.0
2.5
Rise Time (t
R
) (20% to 80%)
Full
300
Fall Time (t
F
) (20% to 80%)
Full
300
FCO Propagation Delay (t
FCO
)
Full
2.0
2.5
DCO Propagation Delay (t
CPD
)
3
Full
t
FCO
+
(t
SAMPLE
/20)
DCO to Data Delay (t
DATA
)
3
Full
(t
SAMPLE
/20) 300
(t
SAMPLE
/20)
DCO to FCO Delay (t
FRAME
)
3
Full
(t
SAMPLE
/20) 300
(t
SAMPLE
/20)
Data to Data Skew
(t
DATA-MAX
t
DATA-MIN
)
Wake-Up Time (Standby)
25°C
600
Wake-Up Time (Power Down)
25°C
375
Pipeline Latency
Full
10
Rev. 0 | Page 6 of 52
AD9219-65
Typ
7.7
7.7
2.5
300
300
2.5
t
FCO
+
(t
SAMPLE
/20)
(t
SAMPLE
/20)
(t
SAMPLE
/20)
±50
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
Max
10
3.5
3.5
Min
65
2.0
2.0
Max
10
3.5
3.5
(t
SAMPLE
/20) + 300
(t
SAMPLE
/20) + 300
±150
(t
SAMPLE
/20) 300
(t
SAMPLE
/20) 300
(t
SAMPLE
/20) + 300
(t
SAMPLE
/20) + 300
±150
ps
ps
ps
Full
±50
600
375
10
ns
μs
CLK
cycles
ps
ps rms
CLK
cycles
APERTURE
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
25°C
25°C
25°C
500
<1
1
500
<1
2
1
See the
AN-835 Application Note
, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
2
Can be adjusted via the SPI interface.
3
t
SAMPLE
/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
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