參數(shù)資料
型號(hào)： AD9219ABCPZ-40
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/56頁(yè)
文件大小： 0K
描述： IC ADC 10BIT SRL 40MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
采樣率（每秒）： 40M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 313mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9219
Data Sheet
Rev. E | Page 24 of 56
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9219.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock during the last step.
Refer to the AN-501 Application Note and to the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs at www.analog.com.
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
05
72
6-
03
8
RMS CLOCK JITTER REQUIREMENT
S
NR
(
d
B
)
Figure 57. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 58 and Figure 59, the power dissipated by
the AD9219 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
05
72
6
-07
4
CURR
E
NT
(
m
A)
P
O
WER
(
m
W)
ENCODE (MSPS)
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
180
200
220
240
260
280
300
320
340
360
0
20
40
60
80
100
120
140
15
20
25
30
35
40
10
Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS
0
05
72
6-
0
78
CURRE
NT
(
m
A)
PO
W
E
R
(mW
)
ENCODE (MSPS)
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
20
40
60
80
100
120
140
160
180
200
10
20
30
40
50
60
250
270
290
310
330
350
370
390
Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
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AD9219ABCPZRL7-40 功能描述:IC ADC 10BIT SRL 40MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
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