參數(shù)資料
型號(hào)： AD9216-80PCBZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9216 80MSPS
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 10
采樣率（每秒）： 80M
數(shù)據(jù)接口： 并聯(lián)
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 234mW @ 80MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9216-80
已供物品： 板
相關(guān)產(chǎn)品： AD9216BCPZRL7-105-ND - IC ADC 10BIT DL 105MSPS 64-LFCSP
AD9216BCPZ-105-ND - IC ADC 10BIT DL 105MSPS 64LFCSP
AD9216BCPZ-80-ND - IC ADC 10BIT DUAL 80MSPS 64LFCSP
AD9216BCPZRL7-80-ND - IC ADC 10BIT DUAL 80MSPS 64LFCSP
AD9216
Rev. A | Page 20 of 40
THEORY OF OPERATION
The AD9216 consists of two high performance ADCs that are
based on the AD9215 converter core. The dual ADC paths are
independent, except for a shared internal band gap reference
source, VREF. Each of the ADC paths consists of a proprietary
front end SHA followed by a pipelined, switched-capacitor ADC.
The pipelined ADC is divided into three sections, consisting of
a sample-and-hold amplifier, followed by seven 1.5-bit stages,
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined through the digital
correction logic block into a final 10-bit result. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the respec-
tive clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the flash
ADC output to control a switched capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be config-
ured as ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9216 is a differential switched-
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA
input accepts inputs over a wide common-mode range. An
input common-mode voltage of midsupply is recommended
to maintain optimal performance.
The SHA input is a differential switched-capacitor circuit.
In Figure 41, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependant on the
application. In IF under-sampling applications, any shunt
capacitors should be removed. In combination with the driv-
ing source impedance, they would limit the input bandwidth.
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched, so the common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
H
VIN+
VIN
–
CPAR
T
0.5pF
T
04775-008
0.5pF
Figure 41. Switched-Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common-mode
of the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT
= 1/2 (AVDD + VREF)
REFB
= 1/2 (AVDD VREF)
Span
= 2 × (REFT REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage and,
by definition, the input span is twice the value of the VREF voltage.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as
VCMMIN
= VREF/2
VCMMAX
= (AVDD + VREF)/2
The minimum common-mode input level allows the AD9216
to accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-ended
source may be driven into VIN+ or VIN. In this configuration,
one input accepts the signal, while the opposite input should be
set to midscale by connecting it to an appropriate reference.
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參數(shù)描述
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AD9216BCPZ-105 功能描述:IC ADC 10BIT DL 105MSPS 64LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:1 個(gè)單端，單極；1 個(gè)單端，雙極
AD9216BCPZ-65 功能描述:IC ADC 10BIT DUAL 65MSPS 64LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱(chēng):497-5435-6
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