參數(shù)資料
型號(hào): AD9215BRUZRL7-65
廠商: Analog Devices Inc
文件頁(yè)數(shù): 32/36頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 65MSPS 3V 28TSSOP
設(shè)計(jì)資源: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Interfacing the High Frequency AD8331 to AD9215 (CN0096)
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 10
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 96mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
配用: AD9215BCP-80EBZ-ND - BOARD EVAL FOR AD9215BCP-80
AD9215BCP-65EBZ-ND - BOARD EVAL FOR AD9215BCP-65
AD9215BCP-105EBZ-ND - BOARD EVAL FOR AD9215BCP-105
Data Sheet
AD9215
Rev. B | Page 5 of 36
Table 3. Digital Specifications
AD9215BRU-65/
AD9215BCP-65
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Parameter
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
Full
IV
2.0
V
Low Level Input Voltage
Full
IV
0.8
V
High Level Input Current
Full
IV
650
+10
650
+10
650
+10
A
Low Level Input Current
Full
IV
70
+10
70
+10
70
+10
A
Input Capacitance
Full
V
2
pF
LOGIC OUTPUTS1
DRVDD = 2.5 V
High Level Output Voltage
Full
IV
2.45
V
Low Level Output Voltage
Full
IV
0.05
V
1
Output voltage levels measured with a 5 pF load on each output.
Table 4. Switching Specifications
AD9215BRU-65/
AD9215BCP-65
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Parameter
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
VI
65
80
105
MSPS
Minimum Conversion Rate
Full
V
5
MSPS
CLOCK Period
Full
V
15.4
12.5
9.5
ns
DATA OUTPUT PARAMETERS
Output Delay1 (tOD)
Full
VI
2.5
4.8
6.5
2.5
4.8
6.5
2.5
4.8
6.5
ns
Pipeline Delay (Latency)
Full
V
5
Cycles
Aperture Delay
25°C
V
2.4
ns
Aperture Uncertainty (Jitter)
25°C
V
0.5
ps rms
Wake-Up Time2
25°C
V
7
ms
OUT-OF-RANGE RECOVERY TIME
25°C
V
1
Cycles
02874-A-002
tA
tPD
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
ANALOG
INPUT
CLK
DATA
OUT
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram
1
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
2
Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB.
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