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參數(shù)資料
| 型號： | AD9214BRSZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 80MSPS 28-SSOP |
| 標準包裝： | 47 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 300mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
REV. D
AD9214
–6–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
OR
CMOS Output; Out-of-Range Indicator. Logic HIGH indicates the analog input voltage was
outside the converter’s range for the current output data.
2
DFS/GAIN
Data Format Select and Gain Mode Select. Connect externally to AVDD for two’s complement
data format and 1 V p-p analog input range. Connect externally to AGND for Offset Binary data
format and 1 V p-p analog input range. Connect externally to REF (Pin 4) for two’s complement
data format and 2 V p-p analog input range. Floating this pin will configure the device for Offset
Binary data format and a 2 V p-p analog input range.
3
REFSENSE
Reference Mode Select Pin for the ADC. This pin is normally connected externally to AGND,
which enables the internal 1.25 V reference, and configures REF (Pin 4) as an analog reference
output pin. Connecting REFSENSE externally to AVDD disables the internal reference, and config-
ures REF (Pin 4) as an external reference input. In this case, the user must drive REF with a clean
and accurate 1.25 V (
±5%) reference input.
4
REF
Reference input or output as configured by REFSENSE (Pin 3). When configured as an output
(REFSENSE = AGND), the internal reference (nominally 1.25 V) is enabled and is available to
the user on this pin. When configured as an input (REFSENSE = AVDD), the user must drive
REF with a clean and accurate 1.25 V (
±5%) reference. This pin should be bypassed to AGND
with an external 0.1
F capacitor, whether it is configured as an input or output.
5, 8, 11
AGND
Analog Ground
6, 7, 12
AVDD
Analog Power Supply, Nominally 3 V
9AIN
Positive terminal of the differential analog input for the ADC.
10
AIN
Negative terminal of the differential analog input for the ADC. This pin can be left open if
operating in single-ended mode, but it is preferable to match the impedance seen at the positive
terminal (see Driving the Analog Inputs).
13
ENCODE
Encode Clock for the ADC. The AD9214 samples the analog signal on the rising edge of ENCODE.
14
PWRDN
CMOS-compatible power-down mode select, Logic LOW for normal operation; Logic HIGH
for power-down mode (digital outputs in high impedance state). PWRDN has an internal
10 k
pull-down resistor to ground.
15, 23
DGND
Digital Output Ground
16, 24
DrVDD
Digital Output Driver Power Supply. Nominally 2.5 V to 3.6 V.
17–22, 25–28
D0 (LSB)–D5,
CMOS Digital Outputs of ADC
D6–D9 (MSB)
PIN CONFIGURATION
28-Lead Shrink Small Outline Package
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9214
PWRDN
ENCODE
AVDD
AGND
AIN
AGND
OR
DFS/GAIN
REFSENSE
REF
AVDD
AGND
DGND
DrVDD
D0 (LSB)
D1
D2
D3
D4
D9 (MSB)
D8
D7
D6
D5
DGND
DrVDD
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