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| 型號： | AD9200ARSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT CMOS 20MSPS 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
AD9200
–16–
REV. E
APPLICATIONS
DIRECT IF DOWN CONVERSION USING THE AD9200
Sampling IF signals above an ADC’s baseband region (i.e., dc
to FS/2) is becoming increasingly popular in communication
applications. This process is often referred to as Direct IF Down
Conversion or Undersampling. There are several potential ben-
efits in using the ADC to alias (i.e., or mix) down a narrowband
or wideband IF signal. First and foremost is the elimination of a
complete mixer stage with its associated amplifiers and filters,
reducing cost and power dissipation. Second is the ability to
apply various DSP techniques to perform such functions as
filtering, channel selection, quadrature demodulation, data
reduction, detection, etc. A detailed discussion on using this
technique in digital receivers can be found in Analog Devices
Application Notes AN-301 and AN-302.
In Direct IF Down Conversion applications, one exploits the
inherent sampling process of an ADC in which an IF signal
lying outside the baseband region can be aliased back into the
baseband region in a similar manner that a mixer will down-
convert an IF signal. Similar to the mixer topology, an image
rejection filter is required to limit other potential interfering
signals from also aliasing back into the ADC’s baseband region.
A tradeoff exists between the complexity of this image rejection
filter and the sample rate as well as dynamic range of the ADC.
The AD9200 is well suited for various narrowband IF sampling
applications. The AD9200’s low distortion input SHA has a
full-power bandwidth extending to 300 MHz thus encompassing
many popular IF frequencies. A DNL of
±0.5 LSB (typ) com-
bined with low thermal input referred noise allows the AD9200 in
the 2 V span to provide 60 dB of SNR for a baseband input sine
wave. Also, its low aperture jitter of 2 ps rms ensures minimum
SNR degradation at higher IF frequencies. In fact, the AD9200
is capable of still maintaining 56 dB of SNR at an IF of 135 MHz
with a 1 V (i.e., 4 dBm) input span. Note, although the AD9200
will typically yield a 3 to 4 dB improvement in SNR when con-
figured for the 2 V span, the 1 V span provides the optimum
full-scale distortion performance. Furthermore, the 1 V span
reduces the performance requirements of the input driver cir-
cuitry and thus may be more practical for system implementa-
tion purposes.
Figure 34 shows a simplified schematic of the AD9200 config-
ured in an IF sampling application. To reduce the complexity of
the digital demodulator in many quadrature demodulation ap-
plications, the IF frequency and/or sample rate are selected such
that the bandlimited IF signal aliases back into the center of the
ADC’s baseband region (i.e., FS/4). For example, if an IF sig-
nal centered at 45 MHz is sampled at 20 MSPS, an image of
this IF signal will be aliased back to 5.0 MHz which corre-
sponds to one quarter of the sample rate (i.e., FS/4). This
demodulation technique typically reduces the complexity of the
post digital demodulator ASIC which follows the ADC.
To maximize its distortion performance, the AD9200 is config-
ured in the differential mode with a 1 V span using a transformer.
The center tap of the transformer is biased at midsupply via a
resistor divider. Preceding the AD9200 is a bandpass filter as
well as a 32 dB gain stage. A large gain stage may be required
to compensate for the high insertion losses of a SAW filter used
for image rejection. The gain stage will also provide adequate
isolation for the SAW filter from the charge “kick back” currents
associated with AD9200’s input stage.
The gain stage can be realized using one or two cascaded
AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz,
current-feedback op amp having a 3rd order intercept character-
ized up to 250 MHz. A passive bandpass filter following the
AD8009 attenuates its dominant 2nd order distortion products
which would otherwise be aliased back into the AD9200’s
baseband region. Also, it reduces any out-of-band noise which
would also be aliased back due to the AD9200’s noise band-
width of 220+ MHz. Note, the bandpass filters specifications
are application dependent and will affect both the total distor-
tion and noise performance of this circuit.
The distortion and noise performance of an ADC at the given
IF frequency is of particular concern when evaluating an ADC
for a narrowband IF sampling application. Both single-tone and
dual-tone SFDR vs. amplitude are very useful in an assessing an
ADC’s noise performance and noise contribution due to aper-
ture jitter. In any application, one is advised to test several units
of the same device under the same conditions to evaluate the
given applications sensitivity to that particular device.
0.1 F
AIN
REFTS
AD9200
REFBS
REFSENSE
VREF
AVDD
200
1k
50
93.1
280
50
22.1
200
SAW
FILTER
OUTPUT
50
BANDPASS
FILTER
G1 = 20dB
G2 = 12dB
L-C
MINI CIRCUITS
T4 - 6T
1:4
0.1 F
1.0 F
Figure 34. Simplified AD9200 IF Sampling Circuit
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| AD9200ARSZRL | 功能描述:IC ADC 10BIT CMOS 20MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD9200JRS | 制造商:Analog Devices 功能描述:ADC Single Pipelined 20Msps 10-bit Parallel 28-Pin SSOP 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 20MSPS 10-BIT PARALLEL 28SSOP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:10-BIT 20 MSPS, 80 MW CMOS A/D CONVERTER - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NW)) |
| AD9200JRSRL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 20Msps 10-bit Parallel 28-Pin SSOP T/R |
| AD9200JRSZ | 功能描述:IC ADC 10BIT CMOS 20MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9200JRSZRL | 功能描述:IC ADC 10BIT CMOS 20MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):16 采樣率（每秒）:15 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:480µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:38-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:38-QFN（5x7） 包裝:帶卷 (TR) 輸入數(shù)目和類型:16 個單端，雙極；8 個差分，雙極 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
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