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| 型號： | AD9148-M5372-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/72頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9149, ADL5372 |
| 設計資源： | AD9148-M5372-EBZ Schematic AD9148-M5372-EBZ BOM AD9148-M5372-EBZ Gerber Files |
| 標準包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9148
Rev. B | Page 47 of 72
SAMPLE RATE CLOCK
FPGA
LOW SKEW
CLOCK DRIVER
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
CLK
FRAME
DCI
OUT1
OUT2
SYNC CLOCK
REFCLK/SYNC
CLK
FRAME
DCI
REFCLK/SYNC
MATCHED
LENGTH TRACES
08910-
054
Figure 55. Typical Circuit Diagram for Synchronizing Devices to a System Clock
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock to CLK, a
separate REFCLK/SYNC input signal is required for synchronization.
To synchronize devices, the CLK signals and the REFCLK/SYNC
signals must be distributed with low skew to all of the devices
being synchronized. This configuration is shown below in
Data Rate Mode Synchronization
The following procedure outlines the steps required to synchronize
multiple devices in data rate mode. The procedure assumes that
the CLK and REFCLK/SYNC signals are applied to all of the
devices. Each individual device must follow the procedure.
The procedure for data rate synchronization when directly
sourcing the DAC sampling clock follows:
1. Configure for data rate, periodic synchronization by
writing 0xC0 to the sync control register (Register 0x10).
Additional synchronization options are available (see the
2. Poll the sync locked bit (Bit 6, Register 0x12) to verify that
the device is back-end synchronized. A high level on this
bit indicates that the clocks are running with a constant
and known phase relative to the sync signal.
3. Reset the FIFO by strobing the FRAME signal for at least the
time interval needed to load complete data to the four DACs
Resetting the FIFO ensures that the correct data is being
read from the FIFO of each of the devices simultaneously.
This completes the synchronization procedure, and at this
stage, all devices should be synchronized.
To ensure that each of the DACs are updated with the correct data
on the same DACCLK edge, two timing relationships must be
met on each DAC. DCI (and data) must meet the setup and hold
times with respect to the rising edge of CLK, and REFCLK/SYNC
must also meet the setup and hold time with respect to the
rising edge of CLK. When resetting the FIFO, the FRAME
signal must be held high for at least the time interval needed to
load complete data to the four DACs (one DCI period for dual-
port mode and two DCI periods for single-port or byte mode).
When these conditions are met, the outputs of the DACs will be
updated within tSKEW + tOUTDLY nanoseconds of each other. A timing
diagram that illustrates the timing requirements of the input
signals is shown in Figure 56.
CLK(1)
CLK(2)
SYNC(2)
FRAME(2)
DCI(2)
tSKEW
tH_DCI
tSU_DCI
tH_SYNC
tSU_SYNC
08910-
055
Figure 56. Synchronization Signal Timing Requirements in Data Rate Mode,
2× Interpolation
Figure 56 shows the synchronization signal timing with 2×
interpolation, so that fDCI = × fCLK. The REFCLK/SYNC input
is shown equal to the DCI rate. The maximum frequency at which
the device can be resynchronized in data rate mode can be
expressed as
N
DATA
SYNC
f
2
=
for any positive integer, N.
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