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參數(shù)資料
| 型號： | AD9117BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/52頁 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 14BIT LO PWR 40LFCSP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計資源： | High CMRR Circuit for Converting Wideband Complementary DAC Outputs to Single-Ended Without Precision Resistors (CN0142) |
| 標準包裝： | 1 |
| 系列： | TxDAC® |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 232mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 125M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
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AD9114/AD9115/AD9116/AD9117
Data Sheet
Rev. C | Page 12 of 52
PIN 1
INDICATOR
1
DB7
2
DB6
3
DB5
4
DB4
5
DVDDIO
6
DVSS
7
DVDD
8
DB3
9
DB2
10
DB1
23 QOUTP
24 RLQP
25 AVSS
26 AVDD
27 RLIP
28 IOUTP
29 IOUTN
30 RLIN
22 QOUTN
21 RLQN
1
DB0
(
L
S
B)
12
NC
13
NC
15
NC
17
CV
DD
16
DCL
KI
O
18
CL
KI
N
19
C
VSS
20
CM
L
Q
14
NC
33
F
S
ADJI
/AUX
I
34
R
E
FIO
35
R
ESET
/PI
N
MD
36
S
CL
K/
CL
KM
D
37
S
D
IO/FOR
M
A
T
38
CS
/P
W
RDN
39
DB9
(
M
S
B)
40
DB8
32
F
S
ADJQ
/AUX
Q
31
CM
L
I
TOP VIEW
(Not to Scale)
AD9115
07466-
004
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
MUST BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 3. AD9115 Pin Configuration
Table 8. AD9115 Pin Function Description
Pin No.
Mnemonic
Description
1 to 4
DB[7:4]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6
DVSS
Digital Common.
7
DVDD
Digital Core Supply Voltage Output (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD
with a 1.0 F capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 10
DB[3:1]
Digital Inputs.
11
DB0 (LSB)
Digital Input (LSB).
12 to 15
NC
No Connect. These pins are not connected to the chip.
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is
disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a resistor, see
the Using the Internal Termination Resistors section. Recommended value for this external resistor is 0 .
21
RLQN
Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24
RLQP
Load Resistor (62.5 ) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
Analog Supply Voltage Input (1.8 V to 3.3 V).
27
RLIP
Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
IOUTN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30
RLIN
Load Resistor (62.5 ) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
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