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參數(shù)資料
| 型號： | AD9054ABSTZ-135 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 135MSPS 44-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ADC Applications ADC Architectures ADC DC/AC Performance |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 135M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 700mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 5 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
AD9054A
–14–
REV. D
Applications that call for the AD9054A to be synchronized at
power-up or only periodically during calibration/reset (i.e., valid
data is not required prior to synchronization), need only be
concerned with the timing of the falling edge of DS. The falling
edge of DS must satisfy the setup time defined by Figure 2 and
the specification table. In this case the DS hold time specifica-
tion on the rising edge can be ignored.
Applications that will continuously update the synchronization
command need to treat the DS signal as a pulse and satisfy
timing requirements on both rising and falling edges. It is easiest
to consider the DS signal in this case to be a pulse train at one
half the encode rate, the positive pulse nominally bracketing the
ENCODE falling edge on alternate cycles as shown in the tim-
ing diagram (Figure 2b). Both the falling and rising edges of DS
must satisfy minimum setup (tSDS) and hold (tHDS) times with
respect to the falling edges of ENCODE. This timing require-
ment produces a tight timing window at higher encode rates.
Synchronization by a single reset edge results in a simpler timing
solution in many applications. For example, synchronization
may be provided at the beginning of each graphics line or frame.
The data are presented at the output of the AD9054A in a ping-
pong (alternating) fashion to optimize the performance of the
converter. It may be aligned for presentation as sixteen bits in
parallel by adding a register stage to the output.
In Dual Channel Mode, the converted data is produced five
clock cycles after the rising edge of ENCODE on which the
sample is taken (five pipeline delays).
In Figure 11, the converter is operating in Dual Port Mode,
with data coming alternately out of Port A and Port B. The
figure illustrates how the output data may be aligned with an
output latch to produce a 16-bit output at 1/2 the conversion
clock rate. The Data Sync input must be properly exercised to
time the A Port with the synchronizing latch.
VIN
0.1 F
1k
0.1 F
NC
CLOCK
VREF OUT
VREF IN
AIN
DEMUX
AD9054A
DS
DS ENC ENC
A PORT
DS
'573
B PORT
'74
DIVIDE
BY 2
NC = NO CONNECT
Figure 11. Dual Port Mode—Aligned Output Data
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| AD9054ABSTZ-200 | 功能描述:IC ADC 8BIT 200MSPS 44-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD9054APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit, 200 MSPS A/D Converter |
| AD9054BST | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-SM-8 BIT ADC |
| AD9054BST-135 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 8BIT ADC SMD 9054 LQFP44 |
| AD9054BST-200 | 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Bit, 200 MSPS A/D Converter |
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