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參數(shù)資料
| 型號： | AD9042D |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 41 MSPS Monolithic A/D Converter |
| 中文描述： | 12位，41 MSPS的單片機的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 488K |
| 代理商： | AD9042D |
AD9042
REV. A
–11–
T HE ORY OF OPE RAT ION
T he AD9042 analog-to-digital converter (ADC) employs a two-
stage subrange architecture. T his design approach ensures
12-bit accuracy, without the need for laser trim, at low power.
As shown in the functional block diagram, the 1 V p-p single-
ended analog input, centered at 2.4 V, drives a single-in to
differential-out amplifier, A1. T he output of A1 drives the first
track-and-hold, T H1. T he high state of the ENCODE pulse
places T H1 in hold mode. T he held value of T H1 is applied to
the input of the 6-bit coarse ADC. T he digital output of the
coarse ADC drives a 6-bit DAC; the DAC is 12 bits accurate.
T he output of the 6-bit DAC is subtracted from the delayed
analog signal at the input to T H3 to generate a residue signal.
T H2 is used as an analog pipeline to null out the digital delay of
the coarse ADC.
T he residue signal is passed to T H3 on a subsequent clock cycle
where the signal is amplified by the residue amplifier, A2, and
converted to a digital word by the 7-bit residue ADC. One bit
of overlap is used to accommodate any linearity errors in the
coarse ADC.
T he 6-bit coarse ADC word and 7-bit residue word are added
together and corrected in the digital error correction logic to
generate the output word. T he result is a 12-bit parallel digital
word which is CMOS-compatible, coded as twos complement.
APPLY ING T HE AD9042
E ncoding the AD9042
T he AD9042 is designed to interface with T T L and CMOS
logic families. T he source used to drive the ENCODE pin(s)
must be clean and free from jitter. Sources with excessive jitter
will limit SNR (ref. Equation 1 under “Noise Floor and SNR”).
0.01μF
TTL OR CMOS
SOURCE
ENCODE
ENCODE
AD9042
Figure 26. Single-Ended TTL/CMOS Encode
T he AD9042 encode inputs are connected to a differential input
stage (see Figure 3 under EQUIVALENT CIRCUIT S). With
no input connected to either the ENCODE or input, the voltage
dividers bias the inputs to 1.6 volts. For T T L or CMOS usage,
the encode source should be connected to ENCODE.
ENCODE
should be decoupled using a low inductance or
microwave chip capacitor to ground. Devices such as AVX
05085C103MA15, a 0.01
μ
F capacitor, work well.
If a logic threshold other than the nominal 1.6 V is required, the
following equations show how to use an external resistor, R
X
, to
raise or lower the trip point (see Figure 3; R1 = 17k, R2 = 8k).
V
1
=
5
R
2
R
X
R
1
R
2
+
R
1
R
X
+
R
2
R
X
to lower logic threshold.
0.01μF
ENCODE
SOURCE
ENCODE
ENCODE
AD9042
R
X
V
l
+5V
R1
R2
Figure 27. Lower Logic Threshold for Encode
V
1
=
5
R
2
R
1
R
X
R
1
+
R
X
R
2
+
to raise logic threshold.
0.01μF
ENCODE
SOURCE
ENCODE
ENCODE
AD9042
R
X
V
l
+5V
R1
R2
AV
CC
Figure 28. Raise Logic Threshold for Encode
While the single-ended encode will work well for many
applications, driving the encode differentially will provide
increased performance. Depending on circuit layout and system
noise, a 1 dB to 3 dB improvement in SNR can be realized. It is
not recommended that differential T T L logic be used however,
because most T T L families that support complementary
outputs are not delay or slew rate matched. Instead, it is
recommended that the encode signal be ac-coupled into the
ENCODE and
ENCODE
pins.
T he simplest option is shown below. T he low jitter T T L signal
is coupled with a limiting resistor, typically 100 ohms, to the
primary side of an RF transformer (these transformers are
inexpensive and readily available; part# in Figure 29 is from
Mini-Circuits). T he secondary side is connected to the
ENCODE and
ENCODE
pins of the converter. Since both
encode inputs are self biased, no additional components are
required.
TTL
ENCODE
ENCODE
AD9042
100
T1-1T
Figure 29. TTL Source – Differential Encode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9042ST | 12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042STPCB | 12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042AD | 12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042AST | 12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042CHIPS | 12-Bit, 41 MSPS Monolithic A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9042D/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042DPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 41 MSPS Monolithic A/D Converter |
| AD9042ST | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 41 MSPS Monolithic A/D Converter |
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