
–3–
ORDE RING GUIDE
T emperature
Range
Package
Description
Package
Option
Model
AD9022AQ/BQ –25
°
C to +85
°
C
AD9022AZ/BZ
28-Lead Ceramic DIP
28-Pin Ceramic
Leaded Chip Carrier
Q-28
Z-28
–25
°
C to +85
°
C
AD9022SQ
AD9022SZ
–55
°
C to +125
°
C 28-Lead Ceramic DIP
–55
°
C to +125
°
C 28-Pin Ceramic
Leaded Chip Carrier
Q-28
Z-28
N – 2
N – 1
DATA
OUTPUT
N
N – 3
N
N + 1
ANALOG
IN
t
OD
= 15–27.5 TYPICAL
N + 2
t
OD
ENCODE
t
a
t
a
= 0.7 TYPICAL
AD9022 Timing Diagram
ABSOLUT E MAX IMUM RAT INGS
1
+V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
–V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +1.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V
S
to 0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating T emperature Range
AD9022AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25
°
C to +85
°
C
AD9022SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55
°
C to +125
°
C
Maximum Junction T emperature
2
. . . . . . . . . . . . . . . . +175
°
C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300
°
C
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
NOT ES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
T ypical thermal impedances: “Q” Package (Ceramic DIP):
θ
JC
= 10
°
C/W;
θ
JA
=
35
°
C/W. “Z” Package (Gullwing Surface Mount):
θ
JC
= 13
°
C/W;
θ
JA
= 45
°
C/W.
AD9022
T est
Level
AD9022AQ/AZ
Min T yp
AD9022BQ/BZ
Min T yp
AD9022SQ/SZ
Min T yp
Parameter (Conditions)
T emp
Max
Max
Max
Units
T wo-T one Intermodulation
Distortion Rejection
3
+25
°
C
V
74
74
74
dBc
DIGIT AL OUT PUT S
1
Logic Compatibility
Logic “1” Voltage
Logic “0” Voltage
Output Coding
T T L
T T L
T T L
Full
Full
VI
VI
2.4
2.4
2.4
V
V
0.5
0.5
0.5
Offset Binary
Offset Binary
Offset Binary
POWER SUPPLY
+V
S
Supply Voltage
+V
S
Supply Current
–V
S
Supply Voltage
–V
S
Supply Current
Power Dissipation
Power Supply
Rejection Ratio (PSRR)
4
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
4.75 5.0
5.25
120
–4.95
220
1.9
4.75 5.0
5.25
120
–4.95
220
1.9
4.75 5.0
5.25
120
–4.95
220
1.9
mA
mA
mA
mA
W
100
100
100
–5.45 –5.2
–5.45 –5.2
–5.45 –5.2
180
1.4
180
1.4
180
1.4
Full
V
32
32
32
mV/V
NOT ES
1
AD9022 load is a single LS latch.
2
RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. T ested at 55% duty cycle.
3
Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale.
4
PSRR is sensitivity of offset error to power supply variations within the 5% limits shown.
Specifications subject to change without notice.
REV. B