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參數(shù)資料
| 型號(hào)： | AD9012SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | High Speed 8-Bit TTL A/D Converter |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 141K |
| 代理商： | AD9012SQ |
REV. D
–2–
AD9012–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(+V
S
= +5.0 V; –V
S
= –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)
Test
Level
AD9012AQ/AJ
Min
Typ
AD9012BQ/BJ
Min
Typ
AD9012SQ/SE
Min
Typ
AD9012TQ/TE
Min
Typ
Parameter
Temp
Max
Max
Max
Max
Units
RESOLUTION
8
8
8
8
Bits
DC ACCURACY
Differential Linearity
+25
°
C
Full
+25
°
C
Full
Full
I
VI
I
VI
VI
0.6
0.75
1.0
1.0
1.2
0.4
0.5
0.75
0.5
1.2
0.6
0.75
1.0
1.0
1.2
0.4
0.5
0.75
0.5
1.2
LSB
LSB
LSB
LSB
Integral Linearity
0.6
0.4
0.6
0.4
No Missing Codes
GUARANTEED
GUARANTEED
GUARANTEED
GUARANTEED
INITIAL OFFSET ERROR
Top of Reference Ladder
+25
°
C
Full
+25
°
C
Full
Full
I
VI
I
VI
V
7
15
18
10
13
7
15
18
10
13
7
15
18
10
13
7
15
18
10
13
mV
mV
mV
mV
μ
V/
°
C
Bottom of Reference Ladder
6
6
6
6
Offset Drift Coefficient
25
25
25
25
ANALOG INPUT
Input Bias Current
1
+25
°
C
Full
+25
°
C
+25
°
C
+25
°
C
+25
°
C
I
VI
I
III
V
V
60
200
200
60
200
200
60
200
200
60
200
200
μ
A
μ
A
k
pF
MHz
V/
μ
s
Input Resistance
Input Capacitance
Large Signal Bandwidth
2
Analog Input Slew Rate
3
25
200
16
160
440
25
200
16
160
440
25
200
16
160
440
25
200
16
160
440
18
18
18
18
REFERENCE INPUT
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Input Bandwidth
+25
°
C
VI
V
V
40
80
0.25
10
110
40
80
0.25
10
110
40
80
0.25
10
110
40
80
0.25
10
110
/
°
C
MHz
+25
°
C
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
Aperture Uncertainty (Jitter)
Output Delay (t
)
4, 5
Transient Response
6
Overvoltage Recovery Time
7
Output Rise Time
4
Output Fall Time
4
Output Time Skew
4, 8
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
I
V
V
I
V
V
I
I
V
75
100
3.8
15
4.9
8
8
6.6
3.3
3.0
75
100
3.8
15
4.9
8
8
6.6
3.3
3.0
75
100
3.8
15
4.9
8
8
6.6
3.3
3.0
75
100
3.8
15
4.9
8
8
6.6
3.3
3.0
MSPS
ns
ps
ns
ns
ns
ns
ns
ns
4
11
4
11
4
11
4
11
8.0
4.3
8.0
4.3
8.0
4.3
8.0
4.3
ENCODE INPUT
Logic “1” Voltage
4
Logic “0” Voltage
4
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulsewidth (Low)
9
Encode Pulsewidth (High)
9
Full
Full
Full
Full
+25
°
C
+25
°
C
+25
°
C
VI
VI
VI
VI
V
I
I
2.0
2.0
2.0
2.0
V
V
μ
A
μ
A
pF
ns
ns
0.8
250
400
0.8
250
400
0.8
250
400
0.8
250
400
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
OVERFLOW INHIBIT INPUT
0 V Input Current
Full
VI
200
250
200
250
200
250
200
250
μ
A
AC LINEARITY
10
Effective Bits
11
In-Band Harmonics
dc to 1.23 MHz
dc to 9.3 MHz
dc to 19.3 MHz
Signal-to-Noise Ratio
12
Noise Power Ratio
13
+25
°
C
V
7.5
7.5
7.5
7.5
Bits
+25
°
C
+25
°
C
+25
°
C
+25
°
C
+25
°
C
I
V
V
I
V
48
55
50
44
47.6
37
48
55
50
44
47.6
37
48
55
50
44
47.6
37
48
55
50
44
47.6
37
dBc
dBc
dBc
dBc
dBc
46
46
46
46
DIGITAL OUTPUT
Logic “1” Voltage
Logic “0” Voltage
Full
Full
VI
VI
2.4
2.4
2.4
2.4
V
V
0.4
0.4
0.4
0.4
POWER SUPPLY
14
Positive Supply Current (+5.0 V) +25
°
C
I
VI
I
VI
V
V
I
33
45
48
179
191
33
45
48
179
191
33
45
48
179
191
33
45
48
179
191
mA
mA
mA
mA
mW
mW
mV/V
Full
+25
°
C
Full
+25
°
C
+25
°
C
+25
°
C
Supply Current (–5.2 V)
152
152
152
152
Nominal Power Dissipation
Reference Ladder Dissipation
Power Supply Rejection Ratio
15
955
44
0.85
955
44
0.85
955
44
0.8
955
44
0.8
2.5
2.5
2.5
2.5
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