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參數(shù)資料
| 型號： | AD9012BQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | High Speed 8-Bit TTL A/D Converter |
| 中文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERDIP-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 141K |
| 代理商： | AD9012BQ |
REV. D
AD9012
–6–
APPLICATION INFORMATION
The AD9012 is compatible with all standard TTL logic fami-
lies. However, to operate at the highest encode rates, the sup-
porting logic around the AD9012 will need to be equally fast.
Two possible choices are the AS and the ALS families. Which-
ever of the TTL logic families is used, special care must be
exercised to keep digital switching noise away from the analog
circuits around the AD9012. The two most critical items are the
digital supply lines and the digital ground return.
The input capacitance of the AD9012 is an exceptionally low
16 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the
160 MHz input bandwidth of the AD9012, a hybrid amplifier
like the AD9610/AD9611 will be required. For those applica-
tions that do not require the full input bandwidth of the AD9012,
some of the more traditional monolithic amplifiers, like the
AD846, should work very well. Overall performance with mono-
lithic amplifiers can be improved by inserting a 40
resistor in
series with the amplifier output.
The output data is buffered through the TTL compatible out-
put latches. In addition to the latch propagation delay (t
PD
), all
data is delayed by one clock cycle, before becoming available at
the outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising edge
of the TTL-compatible ENCODE signal (see timing diagram).
The AD9012 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help to improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INHIBIT pin of the AD9012 determines
how the converter handles overrange inputs (AIN
≥
+ V
REF
). In
the “enabled” state (floating at –5.2 V), the OVERFLOW out-
put will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW for overrange inputs, and all other digital out-
puts will be at logic HIGH (nonreturn-to-zero operation).
The AD9012 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTER-
ESIS control pin). This level of performance is extremely impor-
tant in fault sensitive applications such as digital radio (QAM).
Dramatic improvements in comparator design and construction
give the AD9012 excellent dynamic characteristics, namely SNR
(signal-to-noise ratio). The 160 MHz input bandwidth and low
error rate performance give the AD9012 an SNR of 47 dB with
a 1.23 MHz input. High SNR performance is particularly im-
portant in broadcast video applications where signals may pass
through the converter several times before the processing is
complete. Pulse signature analysis, commonly performed in
advanced radar receivers, is another area that is especially
dependent on high quality dynamic performance.
LAYOUT SUGGESTIONS
Designs using the AD9012, like all high-speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high-speed designs. The first require-
ment is for a substantial ground plane around and under the
AD9012. Separate ground plane areas for the digital and analog
components may be useful, but the separate grounds should
be connected together at the AD9012 to avoid the effects of
“ground loop” currents.
The second area that requires an extra degree of attention
involves the three reference inputs, +V
REF
, REF
MID
, and –V
REF
.
The +V
REF
input and the –V
REF
input should both be driven
from a low impedance source (note that the +V
REF
input is
typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REF
MID
input may be useful in im-
proving the integral linearity by correcting any reference ladder
skews.
The reference inputs should be adequately decoupled to ground
through 0.1
μ
F chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1
μ
F and
0.01
μ
F chip capacitors should be very effective.
The analog input signal is brought into the AD9012 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical
connections. Otherwise, aperture delay errors may degrade
converter performance at high frequencies.
100
V
2N3906
OVERFLOW
D
8
(MSB)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
(LSB)
–5.2V
+5.0V
0.01
m
F
0.1
m
F
0.01
m
F
ENCODE
A
IN
A
IN
–V
REF
+V
REF
0.1
m
F
10
V
0.1
m
F
AD741
AD9611
40
V
AD9012
EQUAL
DISTANCE
50
V
TTL
ENCODE
INPUT
ANALOG
INPUT
(0 TO +2V)
1k
V
4k
V
–15V
1.5k
V
50
V
0.1
m
F
NYQUEST
FILTER
Figure 5. Typical Application
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9012SE | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9012SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed 8-Bit TTL A/D Converter |
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| AD9012TE | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed 8-Bit TTL A/D Converter |
| AD9012TE/883B | 制造商:Rochester Electronics LLC 功能描述:IC A/D CONV IC - Bulk |
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