參數(shù)資料
型號: AD9012AQ
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: High Speed 8-Bit TTL A/D Converter
中文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28
封裝: CERDIP-28
文件頁數(shù): 4/8頁
文件大小: 141K
代理商: AD9012AQ
REV. D
AD9012
–4–
PIN FUNCTION DESCRIPTIONS
Pin #
Name
Description
1
1
1
2
DIGITAL +V
S
OVERFLOW INH
One of three positive digital supply pins (nominally +5.0 V).
OVERFLOW INHIBIT controls the data output coding for overvoltage inputs (AIN
+ V
REF
).
1
3
HYSTERESIS
The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a
change from –5.2 V to –2.2 V at the Hysteresis control pin.
The most positive reference voltage for the internal resistor ladder.
One of two analog input pins. Both analog input pins should be connected together.
One of two analog ground pins. Both analog ground pins should be connected together.
TTL level encode command input. ENCODE is rising edge sensitive.
One of three positive digital supply pins (nominally +5.0 V).
One of two analog ground pins. Both analog ground pins should be connected together.
One of two analog input pins. Both analog inputs should be connected together.
The most negative reference voltage for the internal resistor ladder.
The midpoint tap on the internal resistor ladder.
One of three positive digital supply pins (nominally +5.0 V).
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.
Digital data output. D
1
(LSB) is the least significant bit of the digital output word.
Digital data output.
One of two digital ground pins. Both digital grounds pins should be connected together.
One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be
connected together.
One of two digital ground pins. Both digital ground pins should be connected together.
Digital data output.
Digital data output D
8
(MSB) is the most significant bit of the digital output word.
Overflow data output. Logic HIGH indicates an input overvoltage (V
IN
> + V
REF
), if
OVERFLOW INHIBIT is enabled (overflow enabled, floating). See OVERFLOW INHIBIT.
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.
1
4
1
5
1
6
1
7
1
8
1
9
10
11
12
13
14
+V
REF
ANALOG INPUT
ANALOG GROUND
ENCODE
DIGITAL +V
S
ANALOG GROUND
ANALOG INPUT
–V
REF
REF
MID
DIGITAL +V
S
DIGITAL –V
S
15
16–19
20
21, 22
D
1
(LSB)
D
2
–D
5
DIGITAL GROUND
ANALOG –V
S
23
24, 25
26
27
DIGITAL GROUND
D
6
, D
7
D
8
(MSB)
OVERFLOW
28
DIGITAL –V
S
ANALOG
INPUT
OVERFLOW ENABLED (FLOATING)
OF D
l
D
2
D
3
D
4
D
5
D
6
D
7
D
8
OVERFLOW INHIBITED (GND)
OF D
l
D
2
D
3
D
4
D
5
D
6
D
7
D
8
V
IN
+ V
REF
V
IN
< + V
REF
1 0 0 0 0 0 0 0 0
0 X X X X X X X X
0 1 1 1 1 1 1 1 1
0 X X X X X X X X
PIN CONFIGURATIONS
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9012
DIGITAL V
S
+
REF
MID
–V
REF
ANALOG INPUT
ANALOG GROUND
DIGITAL V
S
+
DIGITAL V
S
+
OVERFLOW INH
HYSTERESIS
+V
REF
ENCODE
ANALOG GROUND
ANALOG INPUT
D
1
(LSB)
D
2
D
3
D
4
D
5
DIGITAL GROUND
ANALOG V
S
DIGITAL V
S
OVERFLOW
D
8
(MSB)
D
7
D
6
ANALOG V
S
DIGITAL GROUND
DIGITAL V
S
TOP VIEW
(Not to Scale)
28 27
1
2
3
4
26
25
21
22
23
24
19
20
5
6
7
8
9
10
11
12 13 14 15 16
R
M
17 18
D
3
D
7
D
6
DIGITAL GROUND
ANALOG V
S
ANALOG V
S
DIGITAL GROUND
D
5
ANALOG INPUT
ANALOG GROUND
ENCODE
DIGITAL V
S
+
ANALOG GROUND
ANALOG INPUT
–V
REF
+
R
H
O
D
S
+
D
S
O
D
8
(
D
S
+
D
S
D
1
(
D
2
D
4
AD9012
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