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參數(shù)資料
| 型號： | AD8802ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT 12CH W/SD 20SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 系列： | TrimDAC® |
| 設(shè)置時間： | 600ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 12 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 60µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 12 電壓，單極 |
| 采樣率（每秒）： | 1.7M |
AD8802/AD8804
REV. 0
–10–
;
; This subroutine loads an AD8802/AD8804 DAC from an 8051 microcomputer,
; using the 8051’s serial port in MODE 0 (Shift Register Mode).
; The DAC value is stored at location DAC_VAL
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
;
PORT1
DATA
90H
;SFR register for port 1
DAC_VALUE
DATA
40H
;DAC Value
DAC_ADDR
DATA
41H
;DAC Address
SHIFT1
DATA
042H
;high byte of 16-bit answer
SHIFT2
DATA
043H
;low byte of answer
SHIFT_COUNT
DATA
44H
;
ORG
100H
;arbitrary start
DO_8802:
CLR
SCON.7
;set serial
CLR
SCON.6
;data mode 0
CLR
SCON.5
CLR
SCON.1
;clr transmit flag
ORL
PORT1.1,#00001110B
;/RS, /SHDN, /CS high
CLR
PORT1.1
;set the /CS low
MOV
SHIFT1,DAC_ADDR
;put DAC value in shift register
ACALL
BYTESWAP
;
MOV
SBUF,SHIFT2
;send the address byte
ADDR_WAIT:
JNB
SCON.1,ADDR_WAIT
;wait until 8 bits are sent
CLR
SCON.1
;clear the serial transmit flag
MOV
SHIFT1,DAC_VALUE
;send the DAC value
ACALL
BYTESWAP
;
MOV
SBUF,SHIFT2
;
VALU_WAIT:
JNB
SCON.1,VALU_WAIT
;wait again
CLR
SCON.1
;clear serial flag
SETB
PORT1.1
;/CS high, latch data
RET
; into AD8801
;
BYTESWAP:
MOV
SHIFT_COUNT,#8
;Shift 8 bits
SWAP_LOOP:
MOV
A,SHIFT1
;Get source byte
RLC
A
;Rotate MSB to carry
MOV
SHIFT1,A
;Save new source byte
MOV
A,SHIFT2
;Get destination byte
RRC
A
;Move carry to MSB
MOV
SHIFT2,A
;Save
DJNZ
SHIFT_COUNT,SWAP_LOOP
;Done?
RET
END
Listing 1. Software for the 8051 to AD8802/AD8804 Serial Port Interface
+5V
P1.7
P1.6
P1.5
P1.4
1.5
1.6
1.7
PORT 1
8051 C
1.4
CLK
VREFL
SDI
O1
O12
CS
SHDN
GND
AD8804
VDD
VREFH
Figure 25. An AD8802/AD8804-8051
C Interface Using
Parallel Port 1
to start the serial interface process. The DAC address is loaded
into the accumulator and four Rotate Right shifts are per-
formed. This places the DAC address in the 4 MSBs of the ac-
cumulator. The address is then sent to the AD8802/AD8804 via
the SEND_SERIAL subroutine. Next, the DAC value is loaded
into the accumulator and sent to the AD8802/AD8804. Finally,
the Chip Select input is set high to complete the data transfer
Unlike the serial port interface of Figure 24, the parallel port in-
terface only transmits 12 bits to the AD8802/AD8804. Also, the
BYTESWAP subroutine is not required for the parallel inter-
face, because data can be shifted out MSB first. However, the
results of the two interface methods are exactly identical. In
most cases, the decision on which method to use will be deter-
mined by whether or not the serial data port is available for
communication with the AD8802/AD8804.
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