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參數(shù)資料
| 型號(hào)： | AD8802ARU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT 12CH W/SD 20-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | TrimDAC® |
| 設(shè)置時(shí)間： | 600ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 12 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 60µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 12 電壓，單極 |
| 采樣率（每秒）： | 1.7M |
AD8802/AD8804
REV. 0
–11–
; This 8051
C subroutine loads an AD8802 or AD8804 DAC with an 8-bit value,
; using the 8051’s parallel port #1.
; The DAC value is stored at location DAC_VALUE
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
PORT1
DATA
90H
;SFR register for port 1
DAC_VALUE
DATA
40H
;DAC Value
DAC_ADDR
DATA
41H
;DAC Address (0 through 7)
LOOPCOUNT
DATA
43H
;COUNT LOOPS
;
ORG
100H
;arbitrary start
LD_8804:
ORL
PORT1,#11110000B
;set CLK, /CS and /SHDN high
CLR
PORT1.5
;Set Chip Select low
MOV
LOOPCOUNT,#4
;Address is 4 bits
MOV
A,DAC_ADDR
;Get DAC address
RR
A
;Rotate the DAC
RR
A
;address to the Most
RR
A
;Significant Bits (MSBs)
RR
A
;
ACALL
SEND_SERIAL
;Send the address
MOV
LOOPCOUNT,#8
;Do 8 bits of data
MOV
A,DAC_VALUE
ACALL
SEND_SERIAL
;Send the data
SETB
PORT1.5
;Set /CS high
RET
;DONE
SEND_SERIAL:
RLC
A
;Move next bit to carry
MOV
PORT1.7,C
;Move data to SDI
CLR
PORT1.6
;Pulse the
SETB
PORT1.6
;CLK input
DJNZ
LOOPCOUNT,SEND_SERIAL
;Loop if not done
RET;
END
Listing 2. Software for the 8051 to AD8802/AD8804 Parallel Port Interface
An MC68HC11-to-AD8802/AD8804 Interface
Like the 8051
C, the MC68HC11 includes a dedicated serial
data port (labeled SPI). The SPI port provides an easy interface
to the AD8802/AD8804 (Figure 27). The interface uses three
lines of Port D for the serial data, and one or two lines from
Port C to control the SHDN and RS (AD8802 only) inputs.
SDI
CLK
CS
SHDN
RS (AD8802 ONLY)
AD8802/
AD8804*
MC68HC11*
MOSI
SCK
SS
PC0
PC1
(PD3)
(PD4)
(PD5)
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. An AD8802/AD8804-to-MC68HC11 Interface
A software routine for loading the AD8802/AD8804 from a
68HC11 evaluation board is shown in Listing 3. First, the
MC68HC11 is configured for SPI operation. Bits CPHA and
CPOL define the SPI mode wherein the serial clock (SCK) is
high at the beginning and end of transmission, and data is valid
on the rising edge of SCK. This mode matches the requirements
of the AD8802/AD8804. After the registers are saved on the
stack, the DAC value and address are transferred to RAM and
the AD8802/AD8804’s CS is driven low. Next, the DAC’s ad-
dress byte is transferred to the SPDR register, which automati-
cally initiates the SPI data transfer. The program tests the SPIF
bit and loops until the data transfer is complete. Then the DAC
value is sent to the SPI. When transmission of the second byte is
complete, CS is driven high to load the new data and address
into the AD8802/AD8804.
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