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參數(shù)資料
| 型號： | AD8801ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT OCTAL W/SD 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | TrimDAC® |
| 設(shè)置時間： | 600ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 27.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | 1.7M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
REV. A
–4–
AD8801/AD8803
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DAC REGISTER LOAD
1
0
1
0
1
0
+5V
0V
SDI
CLK
CS
VOUT
OCTAL 8-BIT TRIMDAC, WITH SHUTDOWN
Figure 2a. Timing Diagram
AX OR DX
1
0
1
0
1
0
+5V
0V
SDI
(DATA
IN)
CLK
CS
VOUT
±1 LSB
±1 LSB ERROR BAND
tS
tCSW
tCSH
tCL
tCSS
tCH
tDS
tDH
tCS1
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
Figure 2b. Detail Timing Diagram
tS
tRS
±1 LSB
±1 LSB ERROR BAND
1
0
+5V
2.5V
RS
VOUT
RESET TIMING
Figure 2c. Reset Timing Diagram
Table I. Serial-Data Word Format
ADDR
DATA
B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB MSB
LSB
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
1
2
0
OPERATION
The AD8801/AD8803 provides eight channels of programmable
voltage output adjustment capability. Changing the programmed
output voltage of each TrimDAC is accomplished by clocking in
an 11-bit serial data word into the SDI (Serial Data Input) pin.
The format of this data word is three address bits, MSB first,
followed by eight data bits, MSB first. Table I provides the se-
rial register data word format. The AD8801/AD8803 has the
following address assignments for the ADDR decode which de-
termines the location of DAC register receiving the serial regis-
ter data in bits B7 through B0:
DAC # = A2
× 4 + A1 × 2 + A0 + 1
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it possible
to load all eight DACs in as little time as 3
s (12 × 8 × 30 ns).
The exact timing requirements are shown in Figure 2.
The AD8801 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power up. The
AD8803 has both a VREFH and a VREFL pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN that places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply,
VREF inputs, and all 8 outputs. In shutdown mode the DACx
latch settings are maintained. When returning to operational
mode from power shutdown the DAC outputs return to their
previous voltage settings.
MSB
OX
2R
R
P CH
N CH
TO OTHER DACS
R
2R
.
GND
VREFL
LSB
DAC
REGISTER
D6
D0
D7
VREFH
Figure 3. AD8801/AD8803 Equivalent TrimDAC Circuit
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage range is determined by the external refer-
ence connected to VREFH and VREFL pins. See Figure 3 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8801, its VREFL is internally connected to GND and
therefore cannot be offset. VREFH can be tied to VDD and VREFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation that determines the programmed output
voltage is:
VO (Dx) = (Dx)/256 × (VREFH – VREFL) + VREFL
(1)
where Dx is the data contained in the 8-bit DACx latch.
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