參數(shù)資料
型號(hào): AD8612ARUZ
廠商: ANALOG DEVICES INC
元件分類: 運(yùn)動(dòng)控制電子
英文描述: Ultrafast, 4 ns Single-Supply Comparators
中文描述: COMPARATOR, 7000 uV OFFSET-MAX, 4.5 ns RESPONSE TIME, PDSO14
封裝: TSSOP-14
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 243K
代理商: AD8612ARUZ
AD8611/AD8612
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. A | Page 6 of 20
V+
IN+
V–
IN–
QA
QA
GND
LATCH
1
2
3
4
8
7
6
5
AD8611
TOP VIEW
(Not to Scale)
0
QA
V+
1
IN+
2
IN–
3
V–
4
8
QA
7
GND
6
LATCH
5
AD8611
TOP VIEW
(Not to Scale)
0
GND
LEA
V–
INA–
INA+
GND
LEB
V+
INB–
INB+
QA
QA
QB
QB
1
2
3
4
5
6
7
AD8612
TOP VIEW
(Not to Scale)
14
13
12
11
10
9
8
0
Figure 4. 8-Lead Narrow Body SOIC Pin Configuration
Figure 5. 8-Lead MSOP Pin Configuration
Figure 6. 14-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
SOIC and
MSOP
TSSOP
1
10
2
3
4
5
5
6
3, 12
7
1
8
2
14
13
4
11
7
6
8
9
Mnemonic
V+
IN+
IN
V
LATCH
GND
QA
QA
QB
QB
LEA
LEB
INA+
INA
INB+
INB
Description
Positive Supply Terminal.
Noninverting Analog Input of the Differential Input Stage.
Inverting Analog Input of the Differential Input Stage.
Negative Supply Terminal.
Latch Enable Input.
Negative Logic Supply
One of Two Complementary Output for Channel A.
One of Two Complementary Output for Channel A.
One of Two Complementary Output for Channel B.
One of Two Complementary Output for Channel B.
Channel A Latch Enable.
Channel B Latch Enable.
Noninverting Analog Input of the Differential Input Stage for Channel A.
Inverting Analog Input of the Differential Input Stage for Channel A.
Noninverting Analog Input of the Differential Input Stage for Channel B.
Inverting Analog Input of the Differential Input Stage for Channel B.
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