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| 型號： | AD8564ARUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP 7NS FAST QUAD 16-TSSOP |
| 標準包裝： | 1 |
| 類型： | 通用 |
| 元件數(shù)： | 4 |
| 輸出類型： | CMOS，TTL |
| 電壓 - 輸入偏移（最小值）： | 7mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 4µA @ 5V |
| 電流 - 靜態(tài)（最大值）： | 14mA，14mA，7mA |
| CMRR, PSRR（標準）： | 85dB CMRR，80dB PSRR |
| 傳輸延遲（最大）： | 9.8ns |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 764 (CN2011-ZH PDF) |
| 其它名稱： | AD8564ARUZ-REELDKR |
AD8564
Rev. B | Page 9 of 12
APPLICATIONS INFORMATION
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator or amplifier, proper design
and layout techniques should be used to ensure optimal perform-
ance from the AD8564. The performance limits of high speed
circuitry can easily be a result of stray capacitance, improper
ground impedance, or other layout issues.
Minimizing resistance from the source to the input is an important
consideration in maximizing the high speed operation of the
AD8564. Source resistance, in combination with equivalent
input capacitance, may cause a lagged response at the input,
thus delaying the output. The input capacitance of the AD8564,
in combination with stray capacitance from an input pin to
ground, may result in several picofarads of equivalent capaci-
tance. A combination of 3 kΩ source resistance and 5 pF of
input capacitance yields a time constant of 15 ns, which is slower
than the 5 ns capability of the AD8564. Source impedances
should be less than 1 kΩ for the best performance.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 μF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible to the
power supply pins to ground. These capacitors act as a charge
reservoir for the device during high frequency switching.
A ground plane is recommended for proper high speed perform-
ance. This can be created by using a continuous conductive plane
over the surface of the circuit board, only allowing breaks in the
plane for necessary current paths. The ground plane provides a
low inductance ground, eliminating any potential differences at
different ground points throughout the circuit board caused
from ground bounce. A proper ground plane also minimizes
the effects of stray capacitance on the circuit board.
OUTPUT LOADING CONSIDERATIONS
The AD8564 output can deliver up to 40 mA of output current
without any significant increase in propagation delay. The
output of the device should not be connected to more than 20
TTL input logic gates or drive a load resistance less than 100 Ω.
To ensure the best performance from the AD8564, it is important
to minimize capacitive loading of the output of the device.
Capacitive loads greater than 50 pF cause ringing on the output
waveform and reduce the operating bandwidth of the comparator.
Propagation delay also increases with capacitive loads above 100 pF.
INPUT STAGE AND BIAS CURRENTS
The AD8564 uses a PNP differential input stage that enables the
input common-mode range to extend all the way from the
negative supply rail to within 2.2 V of the positive supply rail.
The input common-mode voltage can be found as the average
of the voltage at the two inputs of the device. To ensure the
fastest response time, care should be taken to not allow the
input common-mode voltage to exceed this voltage.
The input bias current for the AD8564 is 4 μA. As with any
PNP differential input stage, this bias current goes to 0 on an
input that is high and doubles on an input that is low. Care should
be taken in choosing resistor values to be connected to the
inputs because large resistors could cause significant voltage
drops due to the input bias current.
The input capacitance for the AD8564 is typically 3 pF. This can
be measured by inserting a large source resistance to the input
and measuring the change in propagation delay.
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