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參數(shù)資料
| 型號： | AD8512ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP JFET 8MHZ DUAL LN 8SOIC |
| 設(shè)計資源： | Precision, Bipolar Configuration for the AD5546/56 DAC (CN0024) Precision, Bipolar, Configuration for AD5547/AD5557 DAC (CN0028) |
| 標準包裝： | 1,000 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 20 V/µs |
| 增益帶寬積： | 8MHz |
| 電流 - 輸入偏壓： | 25pA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 2.2mA |
| 電流 - 輸出 / 通道： | 70mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD8510/AD8512/AD8513
Rev. I | Page 15 of 20
Figure 46 shows a scope plot of the output of the AD8510/AD8512/
AD8513 in response to a 400 mV pulse. The circuit is configured in
positive unity gain (worst case) with a load experience of 500 pF.
TIME (1s/DIV)
V
O
LT
A
GE
(
20
0m
V
/D
IV
)
VSY = ±15V
CL = 500pF
RL =10k
02
72
9-
0
41
Figure 46. Capacitive Load Drive Without Snubber
When the snubber circuit is used, the overshoot is reduced from
55% to less than 3% with the same load capacitance. Ringing is
virtually eliminated, as shown in Figure 47.
TIME (1s/DIV)
VO
LT
AG
E
(
200m
V
/DI
V
)
VSY = ±15V
RL = 10k
CL = 500pF
RS = 100
CS = 1nF
02
72
9-
04
2
Figure 47. Capacitive Load with Snubber Network
Optimum values for RS and CS depend on the load capacitance
and input stray capacitance and are determined empirically.
Table 5 shows a few values that can be used as starting points.
Table 5. Optimum Values for Capacitive Loads
CLOAD
RS (Ω)
CS
500 pF
100
1 nF
2 nF
70
100 pF
5 nF
60
300 pF
OPEN-LOOP GAIN AND PHASE RESPONSE
In addition to their impressive low noise, low offset voltage, and
offset current, the AD8510/AD8512/AD8513 have excellent
loop gain and phase response even when driving large resistive
and capacitive loads.
Compared with Competitor A (see Figure 49) under the same
conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/
AD8513 have more than 8 MHz of bandwidth and a phase margin
of more than 52°.
Competitor A, on the other hand, has only 4.5 MHz of band-
width and 28° of phase margin under the same test conditions.
Even with a 1 nF capacitive load in parallel with the 2 kΩ load
at the output, the AD8510/AD8512/AD8513 show much better
response than Competitor A, whose phase margin is degraded
to less than 0, indicating oscillation.
FREQUENCY (Hz)
G
A
IN
(
d
B
)
10k
–30
–20
–10
100k
0
10
30
1M
10M
50M
40
50
20
60
70
–135
–90
–45
0
45
90
135
180
225
270
315
P
HAS
E
(
D
eg
rees
)
02
72
9-
04
3
VSY = ±15V
RL = 2.5k
CL = 0pF
Figure 48. Frequency Response of the AD8510/AD8512/AD8513
FREQUENCY (Hz)
GA
IN
(
d
B
)
10k
–30
–20
–10
100k
0
10
30
1M
10M
50M
40
50
20
60
70
–135
–90
–45
0
45
90
135
180
225
270
315
P
H
AS
E
(
D
eg
rees)
02
72
9-
0
44
VSY = ±15V
RL = 2.5k
CL = 0pF
Figure 49. Frequency Response of Competitor A
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