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參數(shù)資料
| 型號： | AD842JCHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | Wideband, High Output Current, Fast Settling Op Amp |
| 中文描述： | OP-AMP, 2500 uV OFFSET-MAX, 80 MHz BAND WIDTH, UUC7 |
| 封裝： | DIE-7 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 475K |
| 代理商： | AD842JCHIPS |
AD842
–
7
–
REV. E
OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
AD842 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which com-
prise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the final output value;
(3) the time of recovery from the overload associated with slew-
ing and (4) linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.
–
+
AD842
R
L
2.2 F
0.1 F
–
V
S
OUTPUT
2.2 F
0.1 F
+V
S
10k
INPUT
Figure 21. Offset Nulling (DIP Pinout)
Figure 22. 0.01% Settling Time
2.2 F
0.1 F
AD842
499
499
2.2 F
0.1 F
–
15V
DDD5109
GEPULSE
50
499
1k
499
1k
+15V
HP6263
ERROR
( 15)
OSCILTEK
TEK
TEK
FET PROBE
Figure 23. Settling Time Test Circuit
Figure 23 shows how measurement of the AD842’s 0.01% set-
tling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high-speed propri-
etary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
300
load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp gains the
error from the false summing junction by 15, and it contains a
gain vernier to fine trim the gain.
Figure 24 shows the “l(fā)ong term” stability of the settling charac-
teristics of the AD842 output after a 10 V step. There is no
evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful
layout, avoids these problems by minimizing the effects of tran-
sistor isolation capacitance discharge and thermally induced
shifts in circuit operating points. These problems do not occur
even under high output current conditions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD842JH | 制造商:Rochester Electronics LLC 功能描述:HIGH OUTPUT CURRENT AMP - Bulk |
| AD842JHZ | 制造商:Analog Devices 功能描述:OP Amp Single GP ±18V 12-Pin TO-8 制造商:Analog Devices 功能描述:OP AMP SGL GP 18V 12PIN TO-8 - Rail/Tube |
| AD842JN | 制造商:Rochester Electronics LLC 功能描述:WIDEBAND HIGH SPEED OPAMP - Bulk 制造商:Analog Devices 功能描述:IC OP-AMP HIGH SPEED WIDEBAND |
| AD842JNZ | 功能描述:IC OPAMP GP 80MHZ 100MA 14DIP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.028 V/µs 增益帶寬積:105kHz -3db帶寬:- 電流 - 輸入偏壓:3nA 電壓 - 輸入偏移:100µV 電流 - 電源:3.3µA 電流 - 輸出 / 通道:12mA 電壓 - 電源，單路/雙路(±):2.7 V ~ 12 V，±1.35 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:剪切帶 (CT) 其它名稱:OP481GRUZ-REELCT |
| AD842JQ | 功能描述:IC OPAMP GP 80MHZ 100MA 14CDIP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
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