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| 型號： | AD840KQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Wideband, Fast Settling Op Amp |
| 中文描述： | OP-AMP, 700 uV OFFSET-MAX, 400 MHz BAND WIDTH, CDIP14 |
| 封裝： | HERMETIC SEALED, CERDIP-14 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 463K |
| 代理商： | AD840KQ |
REV. C
–4–
AD8400/AD8402/AD8403–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS–1 k VERSION
(V
DD
= 3 V 10% or 5 V 10%, V
A
= V
DD
, V
B
= 0 V,
–40 C
≤
T
A
≤
+125 C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
Resistor Nonlinearity
2
Nominal Resistance
3
Resistance Tempco
Wiper Resistance
Nominal Resistance Match
R-DNL
R-INL
R
AB
R
AB
/
T
R
W
R/R
AB
R
WB
, V
A
= No Connect
R
WB
, V
A
= No Connect
T
A
= 25
°
C, Model: AD840XYY1
V
AB
= V
DD
, Wiper = No Connect
I
W
= 1 V/R
AB
CH 1 to 2, V
AB
= V
DD
, T
A
= 25
°
C
–
5
–
4
0.8
–
1
±
1.5
1.2
700
53
0.75
+3
+4
1.6
LSB
LSB
k
ppm/
°
C
%
100
2
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
Integral Nonlinearity
4
Differential Nonlinearity
4
N
INL
DNL
DNL
V
W
/
T
V
WFSE
V
WZSE
8
–
6
–
4
–
5
Bits
LSB
LSB
LSB
ppm/
°
C
LSB
LSB
±
2
–
1.5
–
2
25
–
12
6
+6
+2
+5
V
DD
= 5 V
V
= 3 V, T
A
= 25
°
C
Code = 80
H
Code = FF
H
Code = 00
H
Voltage Divider Temperature Coefficent
Full-Scale Error
Zero-Scale Error
–
20
0
0
10
RESISTOR TERMINALS
Voltage Range
Capacitance
6
Ax, Bx
Capacitance
6
Wx
Shutdown Supply Current
7
Shutdown Wiper Resistance
V
A, B, W
C
A, B
C
W
I
A_SD
R
W_SD
0
V
DD
V
pF
pF
μ
A
f = 1 MHz, Measured to GND, Code = 80
H
f = 1 MHz, Measured to GND, Code = 80
H
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0, V
DD
= 5 V
75
120
0.01
50
5
100
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
6
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
R
L
= 2.2 k
to V
DD
I
OL
= 1.6 mA, V
= 5 V
V
IN
= 0 V or 5 V, V
DD
= 5 V
2.4
V
V
V
V
V
V
μ
A
pF
0.8
2.1
0.6
V
DD
–
0.1
0.4
±
1
5
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Power Dissipation (CMOS)
9
Power Supply Sensitivity
V
DD
Range
I
DD
I
DD
P
DISS
PSS
PSS
2.7
5.5
5
4
27.5
0.008
0.13
V
μ
A
mA
μ
W
%/%
%/%
V
IH
= V
DD
or V
IL
= 0 V
V
IH
= 2.4 V or 0.8 V, V
DD
= 5.5 V
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= 5.5 V
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
0.01
0.9
0.0035
0.05
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth
–
3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
Crosstalk
11
BW_1K
THD
W
t
S
e
NWB
C
T
R = 1 k
V
A
= 1 V rms + 2 V dc, V
= 2 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V,
±
1% Error Band
R
WB
= 500
, f = 1 kHz,
RS
= 0
V
A
= V
DD
, V
B
= 0 V
5,000
0.015
0.5
3
–
65
kHz
%
μ
s
nV/
√
Hz
dB
NOTES
1
Typicals represent average readings at 25
°
C and V
DD
= 5 V.
1
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1
positions. R-DNL measures the relative step change from ideal between successive tap positions. See TPC 29 test circuit.
1
I
W
= 500
μ
A for V
DD
= 3 V and I
W
= 2.5 mA for V
DD
= 5 V for 1 k
version.
1
3
V
AB
= V
DD
, Wiper (V
W
) = No Connect.
1
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL Specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
1
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
1
6
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
1
7
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
1
8
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of I
DD
versus logic voltage.
1
9
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V
DD
= 5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
Specifications subject to change without notice.
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