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REV. C
AD8400/AD8402/AD8403
–14–
where
Dx
is the data contained in the 8-bit RDAC# latch, and
R
AB
is the nominal end-to-end resistance. For example, when
V
A
= 0 V and B terminal is open circuit, the following output
resistance values will be set for the following RDAC latch codes
(applies to 10 k
potentiometers):
D
(Dec)
R
WA
( )
Output State
255
128
1
0
89
5,050
10,011
10,050
Full Scale
Midscale (
RS
= 0 Condition)
1 LSB
Zero Scale
The typical distribution of R
AB
from channel to channel matches
within
±
1%. However, device-to-device matching is process lot-
dependent, having a
±
20% variation. The change in R
AB
with
temperature has a positive 500 ppm/
°
C temperature coefficient.
The wiper-to-end-terminal resistance temperature coefficient has
the best performance over the 10% to 100% of adjustment range
where the internal wiper contact switches do not contribute any
significant temperature related errors. The graph in TPC 10 shows
the performance of R
WB
tempco versus code: using the trimmer with
codes below 32 results in the larger temperature coefficients plotted.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A terminal to 5 V and B terminal to
ground produces an output voltage at the wiper starting at zero
volts up to 1 LSB less than 5 V. Each LSB of voltage is equal to
the voltage applied across terminal AB divided by the 256
position resolution of the potentiometer divider. The general
equation defining the output voltage with respect to ground for
any given input voltage applied to terminals AB is:
(
256
Operation of the digital potentiometer in the divider mode results
in more accurate operation over temperature. Here the output
voltage is dependent on the ratio of the internal resistors, not
the absolute value; therefore, the temperature drift improves to
15 ppm/
°
C.
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases due to the contributions of the
CMOS switch wiper resistance becoming an appreciable portion of
the total resistance from Terminal B to the wiper. See TPC 9 for
a plot of potentiometer tempco performance versus code setting.
V
D
D
V
V
W
X
X
AB
B
)
=
×
+
(4)
DIGITAL INTERFACING
The AD8400/AD8402/AD8403 contain a standard SPI compat-
ible three-wire serial input control interface. The three inputs
are clock (CLK),
CS
and serial data input (SDI). The positive-
edge sensitive CLK input requires clean transitions to avoid
clocking incorrect data into the serial input register. For best
results use logic transitions faster than 1 V/
μ
s. Standard logic
families work well. If mechanical switches are used for product
evaluation, they should be debounced by a flip-flop or other
suitable means. The Figure 4 block diagrams show more detail
of the internal digital circuitry. When
CS
is taken active low, the
clock loads data into the 10-bit serial register on each positive
clock edge (see Table II).
RDAC
LATCH
#1
GND
A1
W1
B1
V
DD
AD8400
CS
CLK
8
D7
D0
EN
ADDR
DEC
A1
A0
SDI
DI
REG
D0
D7
SER
a.
RDAC
LATCH
#1
R
AGND
RS
A1
W1
B1
V
DD
AD8402
CS
CLK
D7
D0
RDAC
LATCH
#2
R
A4
W4
B4
D7
D0
EN
ADDR
DEC
A1
A0
SDI
DI
10-BIT
SER
REG
D0
SHDN
DGND
D7
8
b.
RDAC
LATCH
#1
R
AGND
RS
A1
W1
B1
V
DD
AD8403
CS
CLK
SDO
D7
D0
RDAC
LATCH
#4
R
A4
W4
B4
D7
D0
EN
ADDR
DEC
A1
A0
D7
SDI
DO
DI
SER
REG
D0
SHDN
DGND
8
c.
Figure 4. Block Diagrams