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參數(shù)資料
| 型號(hào)： | AD8402ARU50 |
| 元件分類： | 通用總線功能 |
| 英文描述： | 256-Tap, Nonvolatile, I2C-Interface, Digital Potentiometers |
| 中文描述： | 四2輸入與門 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 463K |
| 代理商： | AD8402ARU50 |
REV. C
AD8400/AD8402/AD8403
–16–
The ac characteristics of the RDACs are dominated by the internal
parasitic capacitances and the external capacitive loads. The
–
3 dB
bandwidth of the AD8403AN10 (10k
resistor) measures 600 kHz
at half scale as a potentiometer divider. TPC 22 provides the large
signal BODE plot characteristics of the three available resistor
versions 10 k
, 50 k
, and 100 k
. The gain flatness versus
frequency graph, TPC 25, predicts filter applications performance.
A parasitic simulation model has been developed, and is shown
in Figure 8. Listing I provides a macro model net list for the
10 k
RDAC:
Listing I. Macro Model Net List for RDAC
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA
A
0
{DW/256*90.4E-12+30E-12}
RAW
A
W
{(1-DW/256)*RDAC+50}
CW
W
0
120E-12
RBW
W
B
{DW/256*RDAC+50}
CB
B
0
{(1-DW/256)*90.4E-12+30E-12}
*
.ENDS DPOT
The total harmonic distortion plus noise (THD+N) is measured
at 0.003% in an inverting op amp circuit using an offset ground
and a rail-to-rail OP279 amplifier, Test Circuit 5. Thermal noise is
primarily Johnson noise, typically 9 nV/
√
Hz
for the 10 k
version
at f = 1 kHz. For the 100 k
device, thermal noise becomes
29 nV/
√
Hz
. Channel-to-channel crosstalk measures less than
–
65 dB at f = 100 kHz. To achieve this isolation, the extra ground
pins provided on the package to segregate the individual RDACs
must be connected to circuit ground. AGND and DGND pins
should be at the same voltage potential. Any unused potentio-
meters in a package should be connected to ground. Power
supply rejection is typically
–
35 dB at 10 kHz (care is needed to
minimize power supply ripple in high accuracy applications).
APPLICATIONS
The digital potentiometer (RDAC) allows many of the applications
of trimming potentiometers to be replaced by a solid-state solu-
tion offering compact size and freedom from vibration, shock and
open contact problems encountered in hostile environments.
A
major advantage of the digital potentiometer is its programma-
bility. Any settings can be saved for later recall in system memory.
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and the
rheostat (2-terminal configuration) connections shown in Test
Circuits 1 and 2 (see page 11).
Certain boundary conditions must be satisfied for proper AD8400/
AD8402/AD8403 operation. First, all analog signals must remain
within the 0 to V
DD
range used to operate the single-supply
AD8400/AD8402/AD8403 products. For standard potentiometer
divider applications, the wiper output can be used directly. For
low resistance loads, buffer the wiper with a suitable rail-to-rail
op amp such as the OP291 or the OP279. Second, for ac signals
and bipolar dc adjustment applications, a virtual ground will
generally be needed. Whatever method is used to create the
virtual ground, the result must provide the necessary sink and
source current for all connected loads, including adequate bypass
capacitance. Test Circuit 5 (see page 11) shows one channel of
the AD8402 connected in an inverting programmable gain
amplifier circuit. The virtual ground is set at 2.5 V, which allows
the circuit output to span a
±
2.5 volt range with respect to virtual
ground. The rail-to-rail amplifier capability is necessary for the
widest output swing. As the wiper is adjusted from its midscale
reset position (80
H
) toward the A terminal (code FF
H
), the voltage
gain of the circuit is increased in successfully larger increments.
Alternatively, as the wiper is adjusted toward the B terminal
(code 00
H
), the signal becomes attenuated. The plot in Figure 9
shows the wiper settings for a 100:1 range of voltage gain (V/V).
Note the
±
10 dB of pseudo-logarithmic gain around 0 dB (1 V/V).
This circuit is mainly useful for gain adjustments in the range of
0.14 V/V to 4 V/V; beyond this range the step sizes become very
large and the resistance of the driving circuit can become a
significant term in the gain equation.
INVERTING GAIN
–
V/V
256
128
0
0.1
1.0
10
96
64
32
160
192
224
D
–
Figure 9. Inverting Programmable Gain Plot
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