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參數(shù)資料
| 型號： | AD8402AN10 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 8BIT 10K 2CH 14-DIP |
| 標準包裝： | 25 |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 500 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 3 線 SPI（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 14-PDIP |
| 包裝： | 管件 |
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AD8400/AD8402/AD8403
Rev. E | Page 9 of 32
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS6, 10
Bandwidth 3 dB
BW_1 K
R = 1 kΩ
5,000
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
0.015
%
VW Settling Time
tS
VA = VDD, VB = 0 V, ±1% error band
0.5
μs
Resistor Noise Voltage
eNWB
RWB = 500 Ω, f = 1 kHz, RS = 0
3
nV/√Hz
CT
VA = VDD, VB = 0 V
65
dB
1 Typicals represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. IW = 500 μA for VDD = 3 V and
IW = 2.5 mA for VDD = 5 V for 1 kΩ version.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal.
The remaining resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = 5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD8402AN100 | 制造商:Rochester Electronics LLC 功能描述:DUAL 8-BIT POTENTIOMETER - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR |
| AD8402AN50 | 制造商:Rochester Electronics LLC 功能描述:DUAL 8-BIT POTENTIOMETER - Bulk |
| AD8402-AN50 | 制造商:Analog Devices 功能描述: |
| AD8402ANZ10 | 制造商:Analog Devices 功能描述:Digital Potentiometer 256POS 10KOhm Dual 14-Pin PDIP N 制造商:Analog Devices 功能描述:1-/2-/4-CHANNELDIGITAL POTENTIOMETERS - Rail/Tube 制造商:Analog Devices 功能描述:DUAL 8-BIT POTENTIOMETER 制造商:Analog Devices Inc. 功能描述:Digital Potentiometer ICs DUAL 8-BIT POTENTIOMETER |
| AD8402AR1 | 功能描述:IC POT DIG DUAL 1K 8BIT 14SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標準包裝:3,000 系列:DPP 接片:32 電阻（歐姆）:10k 電路數(shù):1 溫度系數(shù):標準值 300 ppm/°C 存儲器類型:非易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.5 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WFDFN 裸露焊盤 供應商設備封裝:8-TDFN（2x3） 包裝:帶卷 (TR) |
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