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參數(shù)資料
| 型號(hào)： | AD8390ACP-EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Low Power, High Output Current Differential Amplifier |
| 中文描述： | 低功耗，高輸出電流差動(dòng)放大器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 531K |
| 代理商： | AD8390ACP-EVAL |
AD8390
SPECIFICATIONS
V
S
= ±12 V or +24 V, R
L
,
G = 10, PWDN = (1,1), I
ADJ
= NC, V
OCM
= float, T
A
= 25°C, unless otherwise noted.
1, 2
Rev. C | Page 3 of 16
Table 1.
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Large Signal Bandwidth
Peaking
Slew Rate
NOISE/DISTORTION PERFORMANCE
Second Harmonic Distortion
Third Harmonic Distortion
Multitone Power Ratio (26 kHz to 1.1 MHz)
Conditions
V
OUT
= 0.2 V p-p, R
F
= 10 k
V
OUT
= 4 V p-p
V
OUT
= 0.2 V p-p
V
OUT
= 4 V p-p
f
C
= 1 MHz, V
OUT
= 2 V
p-p
f
C
= 1 MHz, V
OUT
= 2 V
p-p
Z
= 100 , P
crest factor (CF) = 5.4
Z
= 100 , P
crest factor (CF) = 5.4
f = 10 kHz
f = 10 kHz
V
+IN
– V
–IN
, V
OCM
= midsupply
V
+IN
– V
–IN
, V
OCM
= float
(V
OS,DM(RTI)
)/(V
IN,CM
)
V
OUT
(V
OS,CM
)/V
OUT
R
L
= 10 , f
C
= 100 kHz
Worst harmonic = –60 dBc
(V
+OUT
+ V
–OUT
)/2, V
OCM
= midsupply
(V
+OUT
+ V
–OUT
)/2, V
OCM
= float
PWDN1, PWDN0 = (1,1); I
ADJ
= V
EE
(1,0); I
ADJ
= V
EE
(0,1); I
ADJ
= V
EE
(0,0); I
ADJ
= V
EE
PWDN1, PWDN0 = (1,1); I
ADJ
= NC
(1,0); I
ADJ
= NC
(0,1); I
ADJ
= NC
(0,0); I
ADJ
= NC
V
OS,DM
/V
S
, V
S
= ±1 V, V
OCM
= midsupply
V
OUT,CM
/V
OCM
Min
40
25
Typ
60
40
0.1
300
–82
–91
–70
Max
Unit
MHz
MHz
dB
V/μs
dBc
dBc
dBc
= 19.8 dBm,
LINE
LINE
Multitone Power Ratio (26 kHz to 2.2 MHz)
= 19.8 dBm,
LINE
LINE
–65
dBc
Voltage Noise (RTI)
Input Current Noise
INPUT CHARACTERISTICS
RTI Offset Voltage (V
OS,DM(RTI)
)
RTI Offset Voltage (V
OS,DM(RTI)
)
±Input Bias Current
Input Offset Current
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Differential Output Voltage Swing
Output Balance Error
Linear Output Current
Output Common-Mode Offset
Output Common-Mode Offset
POWER SUPPLY
Operating Range (Dual Supply)
Operating Range (Single Supply)
Total Quiescent Current
Total Quiescent Current
Power Supply Rejection Ratio (PSRR)
PWDN = 0 (Low Logic State)
PWDN = 1 (High Logic State)
V
OCM
TO ±V
OUT
SPECIFICATIONS
Input Voltage Range
Input Resistance
V
OCM
Accuracy
1
V
OCM
bypassed with 0.1 μF capacitor.
2
See
.
Figure 3
–3.0
–3.0
–0.35
58
43.8
–75
–75
±5
+10
70
1.6
0.996
8
1
±1.0
±1.0
–4.0
±0.05
400
2
64
44.2
60
400
±35
±35
5.2
3.8
2.5
0.57
10.0
6.7
3.8
0.67
76
–11.0 to +10.0
28
1.0
+3.0
+3.0
–7.0
+0.35
44.6
+75
+75
±12
+24
6.5
5.0
3.5
1.0
11.0
8.0
5.0
1.0
1.0
nV/√Hz
pA/√Hz
mV
mV
μA
μA
k
pF
dB
V
dB
mA
mV
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
dB
V
V
V
k
V/V
1.004
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