
REV. 0
–2–
AD8381–SPECIFICATIONS
(@ 25 C, AVCC = 15.5 V, DVCC = 3.3 V, VREFLO = VMID = 7 V, VREFHI = 9.5 V,
T
MIN
= 0 C, T
MAX
= 85 C, unless otherwise noted.)
Model
Conditions
Min
Typ
Max
Unit
VIDEO DC PERFORMANCE
1
VDE
VCME
T
MIN
to T
MAX
DAC Code 450 to 800
DAC Code 450 to 800
–7.5
–3.5
+1.0
+0.5
+7.5
+3.5
mV
mV
REFERENCE INPUTS
VMID Range
2
VMID Bias Current
VREFHI
VREFLO
VREFHI Input Resistance
VREFLO Bias Current
VREFHI Input Current
VFS Range
3
(VREFHI–VREFLO) = 2.5 V
6.25
9.25
77
AVCC
VREFHI
V
μ
A
V
V
k
μ
A
μ
A
V
35
VREFLO
VMID – 0.5
to VREFLO
20
0.01
125
0.07
165
5.75
0
RESOLUTION
Coding
Binary
10
Bits
DIGITAL INPUT CHARACTERISTICS
Input Data Update Rate
CLK to Data Setup Time: t
1
CLK to STSQ Setup Time: t
3
CLK to XFR Setup Time: t
5
CLK to Data Hold Time: t
2
CLK to STSQ Hold Time: t
4
CLK to XFR Hold Time: t
6
C
IN
I
IH
I
IL
V
IH
V
IL
V
TH
CLK Rise and Fall Time = 5 ns
NRZ
100
Ms/s
ns
ns
ns
ns
ns
ns
pF
μ
A
μ
A
V
V
V
0
0
0
5
5
5
3
0.7
0.16
0.6
0.05
2.0
0.08
Threshold Voltage
1.4
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
CLK to VID Delay
4
: t
7
INV to VID Delay
Output Current
Output Resistance
AVCC – VOH, VOL – AGND
50% of VIDx
50% of VIDx
1
15.5
14
75
29
1.3
17.5
16
V
ns
ns
mA
13.5
12
30
VIDEO OUTPUT DYNAMIC PERFORMANCE
Data Switching Slew Rate
Invert Switching Slew Rate
Data Switching Settling Time to 1%
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%
Invert Switching Settling Time to 0.25%
CLK and Data Feedthrough
5
All-Hostile Crosstalk
6
Amplitude
Glitch Duration
T
MIN
to T
MAX
, V
O
= 5 V Step, C
L
= 150 pF
265
410
27
50
33
55
5
V/
μ
s
V/
μ
s
ns
ns
ns
ns
mV p-p
32
75
40
100
50
45
mV p-p
ns
POWER SUPPLY
Supply Rejection (VDE)
DVCC, Operating Range
DVCC, Quiescent Current
AVCC, Operating Range
Total AVCC Quiescent Current
STBY AVCC Current
STBY DVCC Current
AVCCx = +15.5 V
±
1 V
0.6
mV/V
V
mA
V
mA
mA
mA
3
5.5
25
18
40
3
0.1
18
9
33
1.8
0.03
STBY = H
STBY = H
OPERATING TEMPERATURE RANGE
0
85
°
C
NOTES
1
VDE = Differential Error Voltage. VCME = Common-Mode Error Voltage. See the Functional Description section.
2
See Figure 6 in the Functional Description section.
3
VFS = 2
×
(VREFHI–VREFLO). See Functional Description section.
4
Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
5
Measured on one output as CLK is driven and STSQ and XFR are held LOW.
6
Measured on one output as the other five are changing from 000
HEX
to 3FF
HEX
for both states of INV.
Specifications subject to change without notice.