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參數(shù)資料
| 型號(hào)： | AD8381 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| 中文描述： | 快速，高電壓驅(qū)動(dòng)器，6通道輸出DecDriverTM元?dú)?，液晶面板?qū)動(dòng) |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 528K |
| 代理商： | AD8381 |
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REV. 0
AD8381
–5–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
Description
1, 12, 19, 23, NC
24, 43–45
2–11
13
No Connect
DB (0:9)
E/O
Data Input
Even/Odd Select
10-Bit Data Input MSB = DB (9).
The active CLK edge is the rising edge when this input is held HIGH
and it is the falling edge when this input is held LOW.
Data is loaded sequentially on the rising edges of CLK when this input
is HIGH and loaded on the falling edges when this input is LOW.
A new data loading sequence begins on the left, with Channel 0, when this
input is LOW, and on the right, with Channel 5 when this input is HIGH.
When this pin is HIGH, the analog output voltages are above VMID.
When LOW, the analog output voltages are below VMID.
This pin is normally connected to the analog ground plane.
Digital Power Supply.
Analog Power Supplies.
14
R/L
Right/Left Select
15
INV
Invert
16
17
18, 27, 31,
35, 42
20
DGND
DVCC
AVCCx
Digital Supply Return
Digital Power Supply
Analog Power Supplies
STBY
Standby
When HIGH, the internal circuits are “debiased” and the power
dissipation drops to a minimum.
A 0.1
μ
F capacitor connected between this pin and AGND ensures
optimum settling time.
These pins are normally connected to the analog ground plane.
21
BYP
Bypass
22, 25, 29,
33, 37, 41
26, 28, 30,
32, 34, 36
38
AGNDx
Analog Supply Returns
VID5, VID4, VID3,
VID2, VID1, VID0
VMID
Analog Outputs
These pins are directly connected to the analog inputs of the LCD panel.
Midpoint Reference
The voltage applied between this pin and AGND sets the midpoint
reference of the analog outputs. This pin is normally connected to VCOM.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
A new data loading sequence begins on the rising edge of CLK when
this input was HIGH on the preceding rising edge of CLK and the E/O
input is held HIGH.
A new data loading sequence begins on the falling edge of CLK when
this input was HIGH on the preceding falling edge of CLK and the E/O
input is held LOW.
Data is transferred to the outputs on the immediately following falling
edge of CLK when this input is HIGH on the rising edge of CLK.
Clock Input.
39
40
46
VREFLO
VREFHI
STSQ
Full-Scale Reference
Full-Scale Reference
Start Sequence
47
XFR
Data Transfer
48
CLK
Clock
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
VID0
AVCC0, 1
VID1
AGND1, 2
VID2
AVCC2, 3
VID3
AGND3, 4
VID4
AVCC4, 5
VID5
AGND5
NC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
NC
NC = NO CONNECT
AD8381
E
R
I
D
D
A
N
S
B
A
N
N
A
V
V
V
A
A
N
N
N
S
X
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8381AST | Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8381AST-REEL | Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8390 | Low Power, High Output Current Differential Amplifier |
| AD8390ACP-EVAL | Low Power, High Output Current Differential Amplifier |
| AD8390ACP-REEL | Low Power, High Output Current Differential Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8381AST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8381AST-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, High Voltage Drive, 6-Channel Output DecDriverTM Decimating LCD Panel Driver |
| AD8381-EB | 制造商:Analog Devices 功能描述:LCD DRVR 9 TO 18V - Bulk |
| AD8381JST | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD8381JSTZ | 制造商:Analog Devices 功能描述: |
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