參數(shù)資料
型號(hào): AD8330ACPZ-R2
廠商: Analog Devices Inc
文件頁(yè)數(shù): 21/32頁(yè)
文件大小: 0K
描述: IC AMP VGA 150MHZ LN LP 16LFCSP
標(biāo)準(zhǔn)包裝: 250
放大器類型: 可變?cè)鲆?br>
電路數(shù): 1
輸出類型: 差分,滿擺幅
轉(zhuǎn)換速率: 1500 V/µs
-3db帶寬: 150MHz
電流 - 輸入偏壓: 100nA
電流 - 電源: 20mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 帶卷 (TR)
配用: AD8330-EVALZ-ND - BOARD EVAL FOR AD8330
AD8330
Data Sheet
Rev. F | Page 28 of 32
EVALUATION BOARD
GENERAL DESCRIPTION
The AD8330-EVALZ is an easy-to-use accessory that enables a
hands-on evaluation of the AD8330 variable gain amplifier
(VGA). It includes test pins for connections to all of the functional
device inputs. Figure 69 is a full size photograph of the board.
03217-
070
Figure 69. Photograph of the AD8330 Evaluation Board
BASIC OPERATION
The input SMA connector IN is terminated with a 49.9
resistor (see Figure 70). For convenience, the board includes an
AD8131 high speed differential amplifier to convert a single-
ended signal source to the differential input of the AD8330. If
desired, the AD8131 can be removed and the AD8330 can be
driven at one of its inputs from a single-ended source.
The AD8330 output is observed at the SMA connectors OUT_HI
and OUT_LO or by using the 2-pin header OUT_HI/ OUT_LO
adjacent to the device.
The AD8330 requires only a +5 V power supply; however, because
of the AD8131 buffer bipolar power supply requirements, ±5 V
supplies are required to power the board. The current required
for the board is approximately 40 mA from the +5 V supply and
10 mA from the 5 V supply.
03217-
071
8
7
2
3
9
GAIN_SLOPE
C5
0.1F
C3
0.1F
INLO
MODE
VPSI
INHI
VPSO
CMOP
OPLO
CNTR
OFST
OPHI
8
ENBL
VPOS
+5V
1
6
5
4
15
16
14
13
COMM
VMAG
VDBS
CMGN
12
11
10
C2
0.1F
UP
C18
0.1F
+5V
C6
0.1F
IN
+5V
C7
0.1F
CMGN
VDBS
VMAG
C10
0.1F
C19
0.1F
C11
0.1F
C4
0.1F
+5V
C14
10nF
C15
0.1F
CNTR
ENBL
3
4
5
6
1
2
C16
10nF
C20
0.1F
C17
10F
10V
–5V
GND1 GND2 GND3 GND4
FLTR
C9
12pF
C8
12pF
C12
0.1F
R4
0
R2
49.9
R1
24.9
OUT_HI
OUT_ LO
R3
1k
OUT_TEST
IN_TEST
C1
10F
10V
+
OFST
C13
1nF
DOWN
+
A1
DUT1
AD8330
FILTER_OFFSET
AD8131
Figure 70. Schematic Diagram
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