- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10572 > AD8328ACPZ (Analog Devices Inc)IC LINE DRIVE CABLE 5V 20-LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD8328ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DRIVE CABLE 5V 20-LFCSP |
| 產(chǎn)品變化通告： | AD8328 Discontinuation 02/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 線路驅(qū)動(dòng)器，發(fā)射器 |
| 應(yīng)用： | 調(diào)制解調(diào)器，機(jī)頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 管件 |
AD8328
Rev. A | Page 10 of 20
APPLICATIONS
GENERAL APPLICATIONS
The AD8328 is primarily intended for use as the power
amplifier (PA) in Data Over Cable Service Interface Specification
(DOCSIS)-certified cable modems and CATV set-top boxes.
The upstream signal is either a QPSK or QAM signal generated
by a DSP, a dedicated QPSK/QAM modulator, or a DAC. In all
cases, the signal must be low-pass filtered before being applied
to the PA to filter out-of-band noise and higher order
harmonics from the amplified signal.
Due to the varying distances between the cable modem and the
head-end, the upstream PA must be capable of varying the
output power by applying gain or attenuation. The ability to
vary the output power of the AD8328 ensures that the signal
from the cable modem has the proper level once it arrives at the
head-end. The upstream signal path commonly includes a
diplexer and cable splitters. The AD8328 has been designed to
overcome losses associated with these passive components in
the upstream cable path.
CIRCUIT DESCRIPTION
The AD8328 is composed of three analog functions in the
power-up or forward mode. The input amplifier (preamp) can
be used single-ended or differentially. If the input is used in the
differential configuration, it is imperative that the input signals
be 180° out of phase and of equal amplitude. A vernier is used
in the input stage for controlling the fine 1 dB gain steps. This
stage then drives a DAC, which provides the bulk of the
AD8328’s attenuation. The signals in the preamp and DAC gain
blocks are differential to improve the PSRR and linearity. A
differential current is fed from the DAC into the output stage.
The output stage maintains 300 Ω differential output impedance,
which maintains proper match to 75 Ω when used with a 2:1
balun transformer.
VIN+
VIN–
VCC
GND
AD8328
BYP
RL
5V
VIN
VOUT+
VOUT–
1
2
1
2
03
15
8-
0
19
Figure 19. Characterization Circuit
SPI PROGRAMMING AND GAIN ADJUSTMENT
The AD8328 is controlled through a serial peripheral interface
(SPI) of three digital data lines: CLK, DATEN, and SDATA.
Changing the gain requires eight bits of data to be streamed into
the SDATA port. The sequence of loading the SDATA register
begins on the falling edge of the DATEN pin, which activates
the CLK line. With the CLK line activated, data on the SDATA
line is clocked into the serial shift register on the rising edge of
the CLK pulses, MSB first. The 8-bit data-word is latched into
the attenuator core on the rising edge of the DATEN line. This
provides control over the changes in the output signal level. The
serial interface timing for the AD8328 is shown in Figure 3 and
Figure 4. The programmable gain range of the AD8328 is
28 dB to +31 dB with steps of 1 dB per least significant bit
(LSB). This provides a total gain range of 59 dB. The AD8328
was characterized with a differential signal on the input and a
TOKO 458PT-1087 2:1 transformer on the output. The AD8328
incorporates supply current scaling with gain code, as shown in
Figure 18. This allows reduced power consumption when
operating in lower gain codes.
INPUT BIAS, IMPEDANCE, AND TERMINATION
The VIN+ and VIN inputs have a dc bias level of VCC/2; therefore,
the input signal should be ac-coupled as shown in Figure 20.
The differential input impedance of the AD8328 is approximately
1.6 kΩ, while the single-ended input is 800 Ω. The high input
impedance of the AD8328 allows flexibility in termination and
properly matching filter networks. The AD8328 exhibits
optimum performance when driven with a pure differential
signal.
OUTPUT BIAS, IMPEDANCE, AND TERMINATION
The output stage of the AD8328 requires a bias of 5 V. The 5 V
power supply should be connected to the center tap of the
output transformer. In addition, the VCC applied to the center
tap of the transformer should be decoupled as seen in Figure 20.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8321ARZ-REEL | IC LINE DVR CATV 20-SOIC T/R |
| MAX11614EEE+ | IC ADC SERIAL 12BIT 8CH 16-QSOP |
| MAX11210EEE+ | IC ADC 24BIT SPI/SRL 5SPS 16QSOP |
| MAX1111EEE+ | IC ADC 8BIT LP 16-QSOP |
| MAX1108EUB+ | IC ADC 8BIT LP 10-UMAX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8328ACPZ-REEL | 功能描述:IC LINE DRIVE CBLE 5V 20LFCSP TR RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8328ACPZ-REEL7 | 功能描述:IC LINE DRIVE CBLE 5V 20LFCSP TR RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8328ARQ | 功能描述:IC LINE DRIVE CABLE 5V 20-QSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8328ARQ-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V Upstream Cable Line Driver |
| AD8328ARQ-REEL | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 5.25V 20-Pin QSOP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。