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參數(shù)資料
| 型號： | AD8328ACP-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5 V Upstream Cable Line Driver |
| 中文描述： | LINE DRIVER, QCC20 |
| 封裝： | LFCSP-20 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 542K |
| 代理商： | AD8328ACP-REEL |
REV. 0
–4–
AD8328
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V
Input Voltage
VIN+, VIN
–
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V p-p
DATEN
, SDATA, CLK,
SLEEP
, TXEN . . . . . . . . . . . . . . . . . . . .
–
0.8 V to +5.5 V
Internal Power Dissipation
QSOP, LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW
Operating Temperature Range . . . . . . . . . . .
–
40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . .
–
65
°
C to +150
°
C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . 300
°
C
*
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8328 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
20-Lead
QSOP
ORDERING GUIDE
Model
Temperature Range
–
40
°
C to +85
°
C
–
40
°
C to +85
°
C
Package Description
θ
JA
83.2
°
C/W
1
83.2
°
C/W
1
Package Option
AD8328ARQ
AD8328ARQ-REEL
AD8328ARQ-EVAL
AD8328ACP
AD8328ACP-REEL
AD8328ACP-EVAL
20-Lead QSOP
20-Lead QSOP
Evaluation Board
20-Lead LFCSP
20-Lead LFCSP
Evaluation Board
RQ-20
RQ-20
–
40
°
C to +85
°
C
–
40
°
C to +85
°
C
30.4
°
C/W
2
30.4
°
C/W
2
CP-20
CP-20
1
Thermal Resistance measured on SEMI standard 4-layer board.
2
Thermal Resistance measured on SEMI standard 4-layer board, paddle soldered to board.
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD8328
TXEN
SDATA
V
CC
CLK
V
IN+
V
IN–
SLEEP
BYP
NC
V
OUT
+
NC = NO CONNECT
GND
GND
GND
GND
RAMP
V
OUT
–
GND
V
CC
DATEN
GND
20-Lead
LFCSP
TOP VIEW
(Not to Scale)
AD8328
1
2
3
4
5
15
14
13
12
11
16
17
20 19 18
6
7
8
9
10
S
GND
GND
GND
V
IN+
V
IN–
G
G
V
C
V
C
T
G
D
S
C
RAMP
V
OUT
+
V
OUT
–
BYP
NC
PIN FUNCTION DESCRIPTIONS
Pin No.
20-Lead
LFCSP
Pin No.
20-Lead
QSOP
Mnemonic
Description
1 ,2, 5,
9, 18, 19
17, 20
3
4
6
1, 3, 4, 7,
11, 20
2, 19
5
6
8
GND
Common External Ground Reference
V
CC
V
IN+
V
IN
–
DATEN
Common Positive External Supply Voltage. A 0.1
μ
F capacitor must decouple each pin.
Noninverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1
μ
F capacitor.
Inverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1
μ
F capacitor.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1
transition transfers the latched data to the attenuator core (updates the gain) and simultaneously
inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous
gain state) and simultaneously enables the register for serial data load.
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.
This requires the input serial data-word to be valid at or before this clock transition.
Low Power Sleep Mode. In the Sleep mode, the AD8328
’
s supply current is reduced to 20
μ
A. A Logic 0
powers down the part (High Z
OUT
State), and a Logic 1 powers up the part.
Internal Bypass. This pin must be externally ac-coupled (0.1
μ
F capacitor).
Negative Output Signal
Positive Output Signal
External RAMP Capacitor (optional)
Logic 0 disables forward transmission. Logic 1 enables forward transmission.
7
9
SDATA
8
10
CLK
10
12
SLEEP
12
13
14
15
16
14
15
16
17
18
BYP
V
OUT
–
V
OUT+
RAMP
TXEN
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD8328ACP-REEL7 | 功能描述:IC LINE DRIVE CBLE 5V 20LFCSP TR RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8328ACPZ | 功能描述:IC LINE DRIVE CABLE 5V 20-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8328ACPZ-REEL | 功能描述:IC LINE DRIVE CBLE 5V 20LFCSP TR RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8328ACPZ-REEL7 | 功能描述:IC LINE DRIVE CBLE 5V 20LFCSP TR RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8328ARQ | 功能描述:IC LINE DRIVE CABLE 5V 20-QSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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