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參數(shù)資料
| 型號(hào)： | AD8324 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3.3 V Upstream Cable Line Driver |
| 中文描述： | 3.3伏上行電纜線路驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 516K |
| 代理商： | AD8324 |
AD8324
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
Rev. 0 | Page 6 of 16
TOP VIEW
(Not to Scale)
AD8324
1
2
3
4
5
15
14
13
12
11
16
17
20 19 18
6
7
8
9
10
GND
GND
GND
V
IN+
V
IN
–
G
G
V
C
V
C
T
G
S
D
S
C
RAMP
V
OUT+
V
OUT
–
BYP
NC
0
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD8324
TXEN
SDATA
V
CC
CLK
V
IN+
V
IN
–
SLEEP
BYP
NC
V
OUT+
NC = NO CONNECT
GND
GND
GND
GND
GND
RAMP
V
OUT
–
GND
V
CC
DATEN
0
Figure 5. 20-Lead LFCSP
Figure 6. 20-Lead QSOP
Table 5. Pin Function Descriptions
Pin No.
Pin No.
20-Lead
LFCSP
QSOP
1, 2, 5, 9,
18, 19
11, 20
17, 20
2, 19
3
5
20-Lead
Mnemonic
GND
Description
Common External Ground Reference.
1, 3, 4, 7,
V
CC
V
IN+
Common Positive External Supply Voltage.
Noninverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1 μF
capacitor.
Inverting Input. DC-biased to approximately V
CC
/2. Should be ac-coupled with a 0.1 μF capacitor.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A
Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and
simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data
latch (holds the previous and simultaneously enables the register for serial data load).
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (most significant bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-
slave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit
to the slave. This requires the input serial data-word to be valid at or before this clock transition.
Low Power Sleep Mode. In the sleep mode, the AD8324’s supply current is reduced to 30 μA. A
Logic 0 powers down the part (high Z
OUT
state), and a Logic 1 powers up the part.
Internal Bypass. This pin must be externally decoupled (0.1 μF capacitor).
Negative Output Signal. Must be biased to V
CC
. See Figure 23.
Positive Output Signal. Must be biased to V
CC
. See Figure 23.
External RAMP Capacitor (Optional).
Logic 0 disables forward transmission. Logic 1 enables forward transmission.
4
6
6
8
V
IN–
DATEN
7
9
SDATA
8
10
CLK
10
12
SLEEP
12
13
14
15
16
14
15
16
17
18
BYP
V
OUT–
V
OUT+
RAMP
TXEN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8324ACP | 3.3 V Upstream Cable Line Driver |
| AD8324ACP-EVAL | 3.3 V Upstream Cable Line Driver |
| AD8324ACP-REEL7 | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ-EVAL | 3.3 V Upstream Cable Line Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8324_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.3 V Upstream Cable Line Driver |
| AD8324ACP | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 3.47V 20-Pin LFCSP EP Tray 制造商:Rochester Electronics LLC 功能描述:+3.3 V UPSTREAM CABLE LINE DRIVER - Bulk |
| AD8324ACP-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.3 V Upstream Cable Line Driver |
| AD8324ACP-R2 | 制造商:Analog Devices 功能描述:+3.3 V UPSTREAM CABLE LINE DRIVER - Tape and Reel |
| AD8324ACP-REEL7 | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 3.47V 20-Pin LFCSP EP T/R |
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