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參數資料
| 型號： | AD8321ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE DVR CATV 20-SOIC T/R |
| 產品變化通告： | AD8321 Discontinuation 02/Mar/2012 |
| 標準包裝： | 1,000 |
| 類型： | 線路驅動器，發(fā)射器 |
| 應用： | 調制解調器，CATV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 配用： | AD8321-EVAL-ND - BOARD EVAL FOR AD8321 |
AD8321
Basic Connection
Input Bias, Impedance and Termination
Figure 25 shows the basic schematic for operating the AD8321
On the input side, the VIN+ and VIN– have a dc bias level
in single-ended inverting mode. To operate in inverting mode,
equal to (VCC/2) – 0.2 V. The input signal must therefore be
connect the input signal through an ac coupling capacitor to
ac-coupled before being applied to either input pin. The input
VIN–; VIN+ should be decoupled to ground with a 0.1
mF
impedance, when operated in single-ended mode is roughly
capacitor. Because the amplifier operates from a single supply,
820
W (900 W in differential mode). An external shunt resis
and the differential input pins are biased to approximately
tance (R1) to ground of 82.5
W is required to create a single-
VCC/2, the differential inputs must be ac-coupled using 0.1
mF
ended input impedance of close to 75
W. If single-ended 50 W
capacitors. For operation in the noninverting mode, the VIN–
termination is required, a 53.6
W shunt resistor may be used.
pin should be decoupled to ground via a 0.1
mF capacitor, with
Differential input operation may be achieved by using a shunt
the input signal being fed to the AD8321 through the (ac-coupled)
resistor of 41
W to ground on each of the inputs, or 82.6 W
VIN+ pin. Inverting mode should be chosen if the AD8321 is
across the inputs resulting in a differential input impedance of
being used as a drop-in replacement for the AD8320 (the
approximately 75
W. Note: to avoid dc loading of either the
AD8321 predecessor). Balanced differential inputs to the
VIN+ or VIN– pin, the ac-coupling capacitor must be placed
AD8321 may also be applied at an amplitude that is one-half
between the input pin(s) and the shunt resistor(s). Refer to the
the specified single-ended input amplitude. See the Differential
Differential Inputs section for more details on this mode of
Inputs section for more on this mode of operation.
operation.
Power Supply and Decoupling
Output Bias, Impedance and Termination
The AD8321 should be powered with a good quality (i.e., low
On the output side, the VOUT pin is also dc-biased to VCC/2 or
noise) single supply of 9 V. Although the AD8321 circuit will
midway between the supply voltage and ground. The output
function at voltages lower than 9 V, optimum performance will
signal must therefore be ac-coupled before being applied to the
not be achieved at lower supply settings. Careful attention must
load. The dc-bias voltage is available on the BYP1 and BYP2
be paid to decoupling the power supply pins. A 10
mF capacitor
pins (Pins 5 and 14 respectively) and can be used in dc-biasing
located in near proximity to the AD8321 is required to provide
schemes. These nodes must be decoupled to ground using a
good decoupling for lower frequency signals. In addition, and
0.1
mF capacitor as shown in Figure 25. If the BYP1 and/or
more importantly, five 0.1
mF decoupling capacitors should be
BYP2 voltages are used externally, they should be buffered.
located close to each of the five power supply pins (7, 8, 9, 17,
External back termination resistors are not required when using
and 20). A 0.1
mF capacitor must also be connected to the pins
the AD8321. The output impedance of the AD8321 is 75
W and
labeled BYP1 and BYP2 (Pins 5 and 14) to provide decoupling
is maintained dynamically. This on chip back termination is
to internal nodes of the device. All six ground pins should be
maintained regardless of whether the amplifier is in forward
connected to a common low impedance ground plane.
transmit mode or reverse powered down mode. If the output
signal is being evaluated on 50
W test equipment such as a
spectrum analyzer, a 75
W to 50 W adapter (commonly called
a minimum loss pad) should be used to maintain a properly
matched circuit.
ATTENUATOR
CORE
DATA SHIFT
REGISTER
DATA LATCH
AD8321
POWER
DOWN/
SWITCH
INTER
DATEN
CLK
VIN+
VIN–
PD
VOUT
SDATA
VCC
C8
0.1
F
VCC
C9
0.1
F
VCC
C10
0.1
F
VCC
C11
0.1
F
BYP1
C5
0.1
F
C2
0.1
F
C1
0.1
F
R1
82.5
INPUT
DATEN
CLK
GND
SDATA
C4
0.1
F
TO
DIPLEXER
RIN = 75
BYP2
VCC
+9V
Ce
0.1
F
C6
10
F
C7
0.1
F
Figure 25. Basic Connection for Single-Ended Inverting Operation
REV. A
–9–
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