參數(shù)資料
型號(hào)： AD8315ACP-REEL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： 50 dB GSM PA Controller
中文描述： SPECIALTY TELECOM CIRCUIT, DSO8
封裝： 2 X 3 MM, LFCSP-8
文件頁(yè)數(shù)： 10/20頁(yè)
文件大小： 1787K
代理商： AD8315ACP-REEL
REV. B
AD8315
–10–
Control Loop Dynamics
In order to understand how the AD8315 behaves in a complete
control loop, an expression for the current in the integration
capacitor as a function of the input V
IN
and the setpoint voltage
V
SET
must be developed. Refer to Figure 3.
SETPOINT
INTERFACE
LOGARITHMIC
RF DETECTION
SUBSYSTEM
3
1
V
SET
RFIN
4
C
FLT
FLTR
7
VAPC
I
SET
= V
SET
/4.15k
I
DET
I
ERR
I
DET
= I
SLP
LOG
10
(V
IN
/V
Z
)
V
SET
V
IN
1.35
Figure 3. Behavioral Model of the AD8315
First, the summed detector currents are written as a function of
the input:
I
I
V
(
V
/
DET
SLP
IN
Z
=
log
)
10
(3)
where
I
DET
is the partially filtered demodulated signal, whose
exact average value will be extracted through the subsequent
integration step;
I
SLP
is the current-mode slope and has a value
of 115
m
A per decade (that is, 5.75
m
A/dB);
V
IN
is the input in
volts-rms; and
V
Z
is the effective intercept voltage, which, as
previously noted, is dependent on waveform but is 316
m
V rms
(–70 dBV) for a sine wave input. Now the current generated by
the setpoint interface is simply:
I
V
k
SET
SET
=
W
/ .15
(4)
The difference between this current and I
DET
is applied to the
loop filter capacitor C
FLT
. It follows that the voltage appearing on
this capacitor, V
FLT
, is the time integral of the difference current:
V
s
I
I
sC
FLT
SET
DET
FLT
( )
(
–
)/
=
(5)
=
W
V
k
I
sC
V
(
V
/
SET
SLP
IN
Z
FLT
/4 15
–
log
)
10
(6)
The control output
V
APC
is slightly greater than this, since the
gain of the output buffer is
￥
1.35. Also, an offset voltage is
deliberately introduced in this stage; this is inconsequential
since the integration function implicitly allows for an arbitrary
constant to be added to the form of Equation 6. The polarity is
such that V
APC
will rise to its maximum value for any value of
V
SET
greater than the equivalent value of V
IN
. In practice, the
V
APC
output will rail to the positive supply under this condition
unless the control loop through the power amplifier is present.
In other words, the AD8315 seeks to drive the RF power to its
maximum value whenever it falls below the setpoint. The use
of exact integration results in a final error that is theoretically
zero, and the logarithmic detection law would ideally result in a
constant response time following a step change of either the
setpoint or the power level, if the power-amplifier control
function were likewise linear-in-dB. This latter condition is
rarely true, however, and it follows that in practice, the loop
response time will depend on the power level, and this effect can
strongly influence the design of the control loop.
Equation 6 can be restated as:
V
V
V
V
(
V
/
sT
APC
SET
SLP
IN
Z
(s
log
)
=
-
10
(7)
where
V
SLP
is the volts-per-decade slope from Equation 1, having
a value of 480 mV/decade, and
T
is an effective time constant for
the integration, being equal to 4.15 k
W
￥
C
FLT
/1.35; the resistor
value comes from the setpoint interface scaling Equation 4 and
the factor 1.35 arises because of the voltage gain of the buffer.
So the integration time constant can be written as:
T
C
in s whenC is
,
in nF
FLT
=
3 07
.
expressed
(8)
To simplify our understanding of the control loop dynamics,
begin by assuming that the power amplifier gain function actu-
ally is linear-in-dB. Also use voltages to express the signals at
the power amplifier input and output, for the moment. Let the
RF output voltage be V
PA
and its input be V
CW
. Further, to
characterize the gain control function, this form is used:
V
G V
PA
CW
V
V
/
APC
GBC
=
10
(
)
(9)
where
G
O
is the gain of the power amplifier when
V
APC
= 0 and
V
GBC
is the gain-scaling. While few amplifiers will conform so
conveniently to this law, it provides a clearer starting point for
understanding the more complex situation that arises when the
gain control law is less ideal.
This idealized control loop is shown in Figure 4. With some
manipulation, it is found that the characteristic equation of this
system is:
V
s
V
(
V
V
V
+
1
kG V
(
V
/
sT
APC
SET
GBC
SLP
GBC
CW
Z
O
( )
)/
–
log
=
)
10
(10)
where
k
is the coupling factor from the output of the power
amplifier to the input of the AD8315 (e.g.,
￥
0.1 for a “20 dB
coupler”), and
T
O
is a modified time constant (
V
GBC
/
V
SLP
)T.
This is quite easy to interpret. First, it shows that a system of
this sort will exhibit a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level
V
SET
or the carrier input
V
CW
. Second, it reveals that the
final value of the control voltage
V
APC
will be determined by
several fixed factors:
(
Example
Assume that the gain magnitude of the power amplifier runs
from a minimum value of
￥
0.316 (–10 dB) at
V
APC
= 0 to
￥
100
(40 dB) at
V
APC
= 2.5 V. Applying Equation 9, G
O
= 0.316 and
V
GBC
= 1 V. Using a coupling factor of
k
= 0.0316 (that is, a
30 dB directional coupler) and recalling that the nominal value of
V
SLP
is 480 mV and
V
Z
= 316 V for the AD8315, first calculate
the range of values needed for
V
SET
to control an output range
of 33 dBm to –17 dBm. This can be found by noting that, in
the steady state, the numerator of Equation 7 must be zero,
that is:
V
t
V
V
V
kG V
(
V
APC
SET
GBC
SLP
CW
Z
=
)
=
(
)
)
/
– log
/
10
(11)
V
V
kV
V
/
SET
SLP
PA
Z
=
log
(
)
10
(12)
when
V
IN
is expanded to
kV
PA
, the fractional voltage sample of
the power amplifier output. Now, for +33 dBm, V
PA
= 10 V rms,
this evaluates to:
V
mV
V
V
SET
(
)
.
log
(
/
)
.
max
=
=
0 48
316
316
1 44
10
m
(13)
For a delivered power of –17 dBm, V
PA
= 31.6 mV rms:
V
mV
V
V
SET
(
)
.
log
(
/
)
.
min
=
=
0 48
1
316
0 24
10
m
(14)
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