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| 型號(hào)： | AD8310ARM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic Amplifier |
| 中文描述： | LOG OR ANTILOG AMPLIFIER, 440 MHz BAND WIDTH, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大?。?/td> | 323K |
| 代理商： | AD8310ARM-REEL7 |
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AD8310
–8–
REV. A
thus alters the intercept. For a 50
reactive match, the voltage
gain is about 4.8 and the whole dynamic range moves down
by 13.6 dB. Finally, note that the effective intercept is function of
waveform. For example, a square-wave input will read 6 dB
higher than a sine wave of the same
amplitude
, and a Gaussian
noise input 0.5 dB higher than a sine wave of the
same
rms valu
e.
Offset Control
In a monolithic log amp, direct-coupling is used between the
stages for several reasons. First, it avoids the need for coupling
capacitors, which may typically have a chip area at least as large
of that of a basic gain cell, thus considerably increasing die size.
Second, the capacitor values predetermine the lowest frequency
at which the log amp can operate; for moderate values, this may
be as high as 30 MHz, limiting the application range. Third, the
parasitic “back-plate” capacitance lowers the bandwidth of the
cell, further limiting the scope of applications.
However, the very high dc gain of a direct-coupled amplifier
raises a practical issue. An offset voltage in the early stages of
the chain is indistinguishable from a “real” signal. If it were as
high as, say, 400
μ
V, it would be 18 dB larger than the smallest
ac signal (50
μ
V), potentially reducing the dynamic range by this
amount. This problem is averted by using a global feedback path
from the last stage to the first, which corrects this offset in a
similar fashion to the dc negative feedback applied around an
op-amp. The high-frequency components of the feedback signal
must, of course, be removed, to prevent a reduction of the HF
gain in the forward path.
An on-chip filter capacitor of 33 pF provides sufficient suppression
of HF feedback to allow operation above 1 MHz. (The –3 dB
point in the high-pass response is at 2 MHz, but the usable range
extends well below this frequency). To further lower the frequency
range, an external capacitor may be added at Pin OFLT. For
example, 300 pF lowers it by a factor of ten; operation at low
audio frequencies requires a capacitor of about 1
μ
F. Note that
this filter has no effect for input levels well above the offset volt-
age, where the frequency range would extend down to dc (for
a signal applied directly to the input pins). The dc offset can
optionally be nulled by adjusting the voltage on the
OFLT pin
(see Applications).
PRODUCT OVERVIEW
The AD8310 comprises six main amplifier/limiter stages. These
six cells, and their and associated g
m
-styled full-wave detectors,
handle the lower two-thirds of the dynamic range. Three “top-end”
detectors, placed at 14.3 dB taps on a passive attenuator, handle
the upper third of the 95 dB range. The first amplifier stage
provides a low-noise spectral-density (1.28 nV/
√
Hz
). Biasing for
these cells is provided by two references: one determines their gain;
the other is a bandgap circuit that determines the logarithmic
slope, and stabilizes it against supply and temperature variations.
The AD8310 may be enabled/disabled by a CMOS-compatible
level at ENBL (Pin 7).
The differential current-mode outputs of the nine detectors are
summed and then converted to single-sided form, nominally scaled
2
μ
A/dB. The output voltage is developed by applying this current
to 3 k
load resistor, followed by a high-speed gain-of-four
buffer amplifier, resulting in a logarithmic slope of 24 mV/dB
(i.e., 480 mV/decade) at VOUT
(Pin 4). The unbuffered voltage
can be accessed at BFIN
(Pin 6), allowing certain functional
modifications, including the addition of an external post-
demodulation filter capacitor, and the alteration or adjustment
of slope and intercept.
+
–
VPOS
INHI
INLO
COMM
3
8mA
1.0k
V
BANDGAP REFERENCE
AND BIASING
SIX 14.3dB 900MHz
AMPLIFIER STAGES
NINSPACED 14.3dB
COINPUT-OFFSET
2
2
m
A
/dB
MIRROR
3k
V
3k
V
1k
V
COMM
COMM
COMM
ENBL
BFIN
VOUT
OFLT
ENABLE
BUFFER
OUTPUT
OFFSET
AD8310
SUPPLY
+INPUT
–INPUT
COMMON
33pF
Figure 20. Main Features of AD8310
The last gain stage also includes an offset-sensing cell. This
generates a bipolarity output current should the main signal
path exhibit an imbalance due to accumulated dc offsets. This
current is integrated by an on-chip capacitor, which may be
increased in value by an off-chip component, at OFLT (Pin
3). The resulting voltage is used to null the offset at the output
of the first stage. Since it does not involve the signal input con-
nections, whose ac coupling capacitors otherwise introduce a
second pole in the feedback path, the stability of the offset
correction loop is assured.
The AD8310 is built
on an advanced dielectrically-isolated
complementary bipolar process.
In the following interface
diagrams, resistors denoted with an uppercase “R” are thin-film
resistors having a low temperature-coefficient of resistance
(TCR) and high linearity under large-signal conditions. Their
absolute tolerance will typically be within
±
20%. Similarly,
capacitors denoted using an uppercase “C,” have a typical
tolerance of
±
15% and essentially zero temperature or voltage
sensitivity. Most interfaces have additional small junction
capacitances associated with them, due to active devices or ESD
protection; these may be neither accurate nor stable. Component
numbering in each of these interface diagrams is local.
Enable Interface
The chip-enable interface is shown in Figure 21. The currents
in the diode-connected transistors control the turn-on and turn-
off states of the band-gap reference and the bias generator, and
are a maximum of 100
μ
A when ENBL is taken to 5 V, under
worst-case conditions. For voltages below 1 V, the AD8310 will
be disabled, and consume a sleep current of under 1
μ
A; tied to
the supply, or a voltage above 2 V, it will be fully enabled. The
internal bias circuitry is very fast (typically <100 ns for either
OFF or ON). In practice, however, the latency period before the
log amp exhibits its full dynamic range is more likely to be lim-
ited by factors relating to the use of ac-coupling at the input or
the settling of the offset-control loop (see following sections).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8310ARMZ | 功能描述:IC LOGARITHMIC AMP 95DB 8-MSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:可變?cè)鲆娣糯笃?應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤(pán) |
| AD8310ARMZ | 制造商:Analog Devices 功能描述:Operational Amplifier (Op-Amp) IC |
| AD8310ARMZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, Voltage-Out DC-440 MHz, 95 dB Logarithmic Amplifier |
| AD8310ARMZ-REEL7 | 功能描述:IC AMP LOGARITHMIC 8MSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:可變?cè)鲆娣糯笃?應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤(pán) |
| AD8310ARMZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fast, Voltage-Out DC-440 MHz, 95 dB Logarithmic Amplifier |
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