參數(shù)資料
型號: AD8303AR
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: +3 V, Dual, Serial Input Complete 12-Bit DAC
中文描述: DUAL, SERIAL INPUT LOADING, 14 us SETTLING TIME, 12-BIT DAC, PDSO14
封裝: 1.75 MM HEIGHT, SOIC-14
文件頁數(shù): 6/16頁
文件大小: 414K
代理商: AD8303AR
AD8303–Typical Performance Characteristics
REV. 0
–6–
120
40
0
2
1
–80
0
80
–120
–40
OUTPUT VOLTAGE – Volts
O
V
DD
= +5V
POSITIVE
CURRENT
LIMIT
NEGATIVE
CURRENT
LIMIT
DATA = 800
H
R
TIED TO
+1.024V
Figure 4. I
OUT
vs. V
OUT
75
0
60
45
30
15
10
100
1M
10k
100k
1k
FREQUENCY – Hz
P
T
A
= +25
°
C
DATA = 800
H
V
DD
= +3V
±
10%
V
DD
= +5V
±
10%
Figure 7. Power Supply Rejection
vs. Frequency
100
90
10
0%
10mV
1μs
2V
V
OUT
CLK
Figure 10. Clock Feedthrough vs.
Time
7
6
00
1
5
3
4
3
5
4
2
LOGIC VOLTAGE – Volts
S
V
DD
= +5V
V
DD
= +3V
T
= +25
°
C
DATA = 000
H
2
1
Figure 6. Supply Current vs. Logic
Input Voltage
100
90
10
0%
1V
5μs
5V
V
OUT
LD
Figure 9. Large Signal Settling Time
2.5
2.0
–0.5
1.5
1.0
0.5
0
–55 –35
125
5
25
45
65
85 105
–15
V
O
TEMPERATURE –
°
C
V
DD
= +2.7V
V
DD
= +5.5V
NO LOAD
SS = 200 UNITS
NORMALIZED TO +25
°
C
Figure 12. Full-Scale Voltage Drift
vs. Temperature
TIME = 100μs/DIV
B
100
90
10
0%
T
= +25
°
C
NBW = 635kHz
Figure 5. Broadband Noise
CODE 800
H
TO 7FF
H
100
90
10
0%
50mV
200ns
5V
V
OUT
LD
Figure 8. Midscale Transition
Performance
120
100
0
20
60
80
40
–5 –3
TOTAL UNADJUSTED ERROR – LSB
1
5
–1
9
F
TUE =
(INL+ZS+FS)
SS = 200 UNITS
V
DD
= +2.7V
3
7
11 13 15
Figure 11. Total Unadjusted
Error Histogram
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