參數(shù)資料
型號(hào)： DS17485SN-5+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 30/31頁(yè)
文件大?。?/td> 0K
描述： IC RTC 5V 4K NV RAM 24-SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 31
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，夏令時(shí)，閏年，NVSRAM，方波輸出
存儲(chǔ)容量： 4KB
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： 并聯(lián)
電源電壓： 4.5 V ~ 5.5 V
電壓 - 電源，電池： 2.5 V ~ 3.7 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 管件
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Real-Time Clocks
8
_____________________________________________________________________
Pin Description (continued)
PIN
24
28
NAME
FUNCTION
13
23
CS
Active-Low Chip-Select Input. This pin must be asserted low during a bus cycle for the
device to be accessed.
CS must be kept in the active state during RD and WR. Bus cycles
that take place without asserting
CS latch addresses, but no access occurs.
14
24
ALE
Address Latch Enable Input, Active High. This input pin is used to demultiplex the
address/data bus. The falling edge of ALE causes the address to be latched within the
device.
15
25
WR
Active-Low Write Input. This pin defines the period during which data is written to the
addressed register.
17
27
RD
Active-Low Read Input. This pin identifies the period when the device drives the bus with
read data. It is an enable signal for the output buffers of the device.
18
28
KS
Active-Low Kickstart Input. When VCC is removed from the device, the system can be
powered on in response to an active-low transition on the
KS pin, as might be generated
from a key closure. VBAUX must be present and auxiliary-battery-enable bit (ABE) must be
set to 1 if the kickstart function is used, and the
KS pin must be pulled up to the VBAUX
supply. While VCC is applied, the
KS pin can be used as an interrupt input. If not used, KS
must be grounded and ABE set to 0.
19
1
IRQ
Active-Low Interrupt Request. This pin is an active-low output that can be used as an
interrupt input to a processor. The
IRQ output remains low as long as the status bit causing
the interrupt is present and the corresponding interrupt-enable bit is set. To clear the
IRQ
pin, the application software must clear all enabled flag bits contributing to the pin’s active
state. When no interrupt conditions are present, the
IRQ level is in the high-impedance
state. Multiple interrupting devices can be connected to an
IRQ bus, provided that they are
all open drain. The
IRQ pin requires an external pullup resistor to VCC.
20
2
VBAT
Connection for Primary Battery. This supply input is used to power the normal clock
functions when VCC is absent. Diodes placed in series between VBAT and the battery can
prevent proper operation. If VBAT is not required, the pin must be grounded. UL recognized
to ensure against reverse charging current when used with a lithium battery (www.maxim-
ic.com/qa/info/ul). This pin is missing (N.C.) on the EDIP package.
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