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參數(shù)資料
| 型號： | DS17485SN-5+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC 5V 4K NV RAM 24-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 31 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，夏令時，閏年，NVSRAM，方波輸出 |
| 存儲容量： | 4KB |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
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The timing associated with both the wake-up and kick-
starting sequences is illustrated in the
Wake-
Up/Kickstart Timing Diagram (Figure 6). The timing
associated with these functions is divided into five inter-
vals, labeled 1 to 5 on the diagram.
The occurrence of either a kickstart or wake-up condition
causes the PWR pin to be driven low, as described
above. During interval 1, if the supply voltage on the
DS17x85/DS17x87 VCC pin rises above the greater of
VBAT or VPF before the power-on timeout period (tPOTO)
expires, then PWR remains at the active-low level. If VCC
does not rise above the greater of VBAT or VPF in this
time, then the PWR output pin is turned off and returns to
its high-impedance level. In this event, the IRQ pin also
remains tri-stated. The interrupt flag bit (either WF or KF)
associated with the attempted power-on sequence
remains set until cleared by software during a subse-
quent system power-on.
If VCC is applied within the timeout period, then the sys-
tem power-on sequence continue as shown in intervals
2 to 5 in the timing diagram. During interval 2, PWR
remains active and IRQ is driven to its active-low level,
indicating that either WF or KF was set in initiating the
power-on. In the diagram KS is assumed to be pulled
up to the VBAUX supply. Also at this time, the PAB bit is
automatically cleared to 0 in response to a successful
power-on. The PWR line remains active as long as the
PAB remains cleared to 0.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Real-Time Clocks
____________________________________________________________________
23
Figure 6. Wake-Up/Kickstart Timing Diagram
Note: Wake-up/kickstart timeout is generated only when the oscillator is enabled and the countdown chain is not reset.
VBAT
VIH
tKSPW
tPOTP
VIH
1
2
3
45
VIL
HIGH-IMPEDANCE
VIL
VPF
0V
*CONDITION
VPF < VBAT
*THIS CONDITION CAN OCCUR WITH THE 3V DEVICE.
NOTE: THE TIME INTERVALS SHOWN ABOVE ARE REFERENCED IN THE WAKE-UP/KICKSTART SECTION.
*CONDITION
VBAT > VPF
WF/KF
(INTERNAL)
KS
PWR
IRQ
Table 6. Wake-Up/Kickstart Timing
(TA =+25°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Kickstart-Input Pulse Width
tKSPW
2s
Wake-Up/Kickstart Power-On
Timeout
tPOTO
2s
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