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參數(shù)資料
| 型號： | AD8230YRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP CHOPPER R-R PREC 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | 斷路器（零漂移） |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 2 V/µs |
| 電流 - 輸入偏壓： | 150pA |
| 電壓 - 輸入偏移： | 20µV |
| 電流 - 電源： | 3.2mA |
| 電流 - 輸出 / 通道： | 15mA |
| 電壓 - 電源，單路/雙路(±)： | 8 V ~ 16 V，±4 V ~ 8 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD8230
Rev. B | Page 12 of 16
TEMPERATURE (°C)
150
–50
0
50
100
O
F
SET
VO
L
T
A
G
E
(
V
R
T
I)
0
–1
–2
–3
–4
–5
RF = 100k, RG = 1k
RF = 10k, RG = 100
05
06
3-
0
33
Figure 33. Effect of Feedback Resistor on Offset Voltage Drift
LEVEL-SHIFTING THE OUTPUT
A reference voltage, as shown in Figure 34, can be used to
level-shift the output. The reference voltage, VR, is limited to
VS + 3.5 V to +VS 2.5 V. (For G < 10, the reference voltage
range is limited to VS + 4.24 V to +VS – 2.75 V.) Otherwise, it
is nominally tied to midsupply. The voltage source used to level-
shift the output should have a low output impedance to avoid
contributing to gain error. In addition, it should be able to
source and sink current. To minimize offset voltage, the VREF
pins should be connected either to the local ground or to a
reference voltage source that is connected to the local ground.
2
6
1
7
5
8
4
3
AD8230
VOUT
–VS
+VS
0.1F
RG
RF
0.1F
VR
05
06
3-
0
34
Figure 34. Level-Shifting the Output
The output can also be level-shifted by adding a resistor, RO, as
shown in Figure 35. The benefit is that the output can be level-
shifted to as low as 100 mV of the negative supply rail and to as
high as 200 mV of the positive supply rail, increasing unipolar
output swing. This can be useful in applications, such as strain
gauges, where the force is only applied in one direction. Another
benefit of this configuration is that a supply rail can be used for
VR’ eliminating the need to add an additional external reference
voltage.
The gain changes with the inclusion of RO. The full expression is
()
'
R
O
F
IN
O
G
O
G
F
R'
O
F
IN
O
G
F
OUT
V
R
V
R
V
R
V
R
V
+
=
+
=
1
2
1
||
2
(3)
The following steps can be taken to set the gain and level-shift
the output:
2. Solve for RO using Equation 4.
LEVEL
DESIRED
F
R'
O
V
R
V
R
×
=
(4)
where:
VR’ is a voltage source, such as a supply voltage.
VDESIRED-LEVEL is the desired output bias voltage.
3. Solve for RG.
1
2
=
F
O
G
R
Gain
R
(5)
2
6
1
7
5
8
4
3
AD8230
VOUT
–VS
+VS
0.1F
RG
RF
RO
0.1F
VR'
0
50
63
-03
5
Figure 35. Level-Shifting the Output Without an
Additional Voltage Reference
2
6
1
7
5
8
4
3
AD8230
VOUT
–5V
+5V
0.1F
203
9.76k
10.2k
0.1F
+5V
0
50
63
-03
6
Figure 36. An AD8230 with its Output Biased at 4.8 V;
G = 100; VDESIRED-LEVEL = 4.8 V
SOURCE IMPEDANCE AND INPUT SETTLING TIME
The input stage of the AD8230 consists of two actively driven,
differential switched capacitors, as described in Figure 30 and
that the associated parasitic capacitances, 70 pF, are balanced
between the inputs to achieve high common-mode rejection.
On each sample period (approximately 85 μs), these parasitic
capacitances must be recharged to the common-mode voltage
by the signal source impedance (10 kΩ maximum). If resistors
and capacitors are used at the input of the AD8230, care should
be taken to maintain close match to maximize CMRR.
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